# XDC constraints for the Xilinx VCU118 board # part: xcvu9p-flga2104-2L-e # General configuration set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] # System clocks # 300 MHz #set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] #set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] #create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] #set_clock_groups -asynchronous -group [get_clocks clk_300mhz -include_generated_clocks] # 250 MHz #set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] #set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] #create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] #set_clock_groups -asynchronous -group [get_clocks clk_250mhz_1 -include_generated_clocks] #set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] #set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] #create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] #set_clock_groups -asynchronous -group [get_clocks clk_250mhz_2 -include_generated_clocks] # 125 MHz set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p] set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks] # 90 MHz #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] #set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks] # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] # Reset button set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports reset] # Push buttons set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports btnu] set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports btnl] set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports btnd] set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports btnr] set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports btnc] # DIP switches set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] # UART set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports uart_rxd] set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports uart_cts] # Gigabit Ethernet SGMII PHY set_property -dict {LOC AU24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_p] set_property -dict {LOC AV24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_n] set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_p] set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_n] set_property -dict {LOC AT22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_p] set_property -dict {LOC AU22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_n] set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports phy_int_n] set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] # 625 MHz ref clock from SGMII PHY #create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] #set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]