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188 lines
7.4 KiB
ReStructuredText
188 lines
7.4 KiB
ReStructuredText
.. _rb_port_ctrl:
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===========================
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Port control register block
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===========================
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The port control register block has a header with type 0x0000C003, version 0x00000200, and contains several port-level control registers.
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.. table::
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======== ============= ====== ====== ====== ====== =============
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Address Field 31..24 23..16 15..8 7..0 Reset value
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======== ============= ====== ====== ====== ====== =============
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RBB+0x00 Type Vendor ID Type RO 0x0000C003
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-------- ------------- -------------- -------------- -------------
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000200
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-------- ------------- ------ ------ ------ ------ -------------
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RBB+0x08 Next pointer Pointer to next register block RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x0C Features Port feature bits RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x10 TX control TX control/status RW 0x00000000
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-------- ------------- ------------------------------ -------------
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RBB+0x14 RX control RX control/status RW 0x00000000
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-------- ------------- ------------------------------ -------------
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RBB+0x18 FC ctrl RX quanta step TX quanta step RW -
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-------- ------------- -------------- -------------- -------------
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RBB+0x1C LFC ctrl ctrl LFC watermark RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x20 PFC ctrl 0 ctrl PFC watermark 0 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x24 PFC ctrl 1 ctrl PFC watermark 1 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x28 PFC ctrl 2 ctrl PFC watermark 2 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x2C PFC ctrl 3 ctrl PFC watermark 3 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x30 PFC ctrl 4 ctrl PFC watermark 4 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x34 PFC ctrl 5 ctrl PFC watermark 5 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x38 PFC ctrl 6 ctrl PFC watermark 6 RW 0x00000000
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-------- ------------- ------ ---------------------- -------------
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RBB+0x3C PFC ctrl 7 ctrl PFC watermark 7 RW 0x00000000
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======== ============= ====== ====================== =============
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See :ref:`rb_overview` for definitions of the standard register block header fields.
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.. object:: Features
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The features field contains all of the port-level feature bits, indicating the state of various optional features that can be enabled via Verilog parameters during synthesis.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x0C Interface feature bits RO -
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======== ============================== =============
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Currently implemented feature bits:
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.. table::
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=== =======================
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Bit Feature
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=== =======================
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0 LFC (IEEE 802.3 annex 31B)
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1 PFC (IEEE 802.3 annex 31D)
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2 Internal MAC control
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=== =======================
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.. object:: TX control/status
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The TX control/status field contains some high-level control and status registers for the transmit side of the link associated with the port.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x10 TX control/status RW 0x00000000
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======== ============================== =============
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Control bits:
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.. table::
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=== =======================
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Bit Function
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=== =======================
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0 TX enable
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8 TX pause control (halt TX traffic)
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16 TX status (link is ready)
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17 TX reset status (MAC TX is in reset)
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24 TX pause req status
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25 TX pause ack status
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=== =======================
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.. object:: RX control/status
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The RX control/status field contains some high-level control and status registers for the receive side of the link associated with the port.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x14 RX control/status RO -
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======== ============================== =============
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Status bits:
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.. table::
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=== =======================
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Bit Function
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=== =======================
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0 RX enable
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8 RX pause control (halt RX traffic)
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16 RX status (link is ready)
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17 RX reset status (MAC RX is in reset)
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24 RX pause req status
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25 RX pause ack status
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=== =======================
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.. object:: FC control
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The FC control field contains the quanta step size per clock cycle in units of 1/256 of one quanta for the internal MAC control layer. Default value is based on the MAC interface width.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x18 RX quanta step TX quanta step RW -
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======== ============== ============== =============
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.. object:: LFC control
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The LFC control field contains control and status registers for link-level flow control (LFC) (IEEE 802.3 annex 31B pause frames).
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x1C ctrl LFC watermark RW 0x00000000
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======== ====== ====================== =============
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control bits:
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.. table::
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=== =======================
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Bit Function
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=== =======================
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24 TX LFC en
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25 RX LFC en
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28 TX LFC req
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29 RX LFC req
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=== =======================
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.. object:: PFC control N
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The PFC control field contains control and status registers for priority flow control (PFC) (IEEE 802.3 annex 31D PFC).
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x20 ctrl PFC watermark RW 0x00000000
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======== ====== ====================== =============
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control bits:
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.. table::
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=== =======================
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Bit Function
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=== =======================
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24 TX PFC en
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25 RX PFC en
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28 TX PFC req
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29 RX PFC req
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=== =======================
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