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590 lines
20 KiB
Verilog
590 lines
20 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2021-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC Interface TX path
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*/
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module mqnic_interface_tx #
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(
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// Structural configuration
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parameter PORTS = 1,
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// PTP configuration
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parameter PTP_TS_WIDTH = 96,
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// Queue manager configuration
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parameter TX_QUEUE_INDEX_WIDTH = 13,
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parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
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parameter CQN_WIDTH = TX_QUEUE_INDEX_WIDTH,
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parameter QUEUE_PTR_WIDTH = 16,
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parameter LOG_QUEUE_SIZE_WIDTH = 4,
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parameter LOG_BLOCK_SIZE_WIDTH = 2,
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// Descriptor management
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parameter TX_MAX_DESC_REQ = 16,
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parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8,
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parameter DESC_SIZE = 16,
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parameter CPL_SIZE = 32,
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parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
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parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
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parameter REQ_TAG_WIDTH = 8,
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parameter DESC_REQ_TAG_WIDTH = 8,
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parameter CPL_REQ_TAG_WIDTH = 8,
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// TX and RX engine configuration
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parameter TX_DESC_TABLE_SIZE = 32,
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parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
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// Interface configuration
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parameter PTP_TS_ENABLE = 1,
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parameter TX_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE)+1,
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parameter TX_CHECKSUM_ENABLE = 1,
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parameter MAX_TX_SIZE = 9214,
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parameter TX_RAM_SIZE = 32768,
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// DMA interface configuration
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parameter DMA_ADDR_WIDTH = 64,
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parameter DMA_LEN_WIDTH = 16,
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parameter DMA_TAG_WIDTH = 16,
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parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE),
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parameter RAM_SEG_COUNT = 2,
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parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
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parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
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parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
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parameter RAM_PIPELINE = 2,
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// Streaming interface configuration
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parameter AXIS_DATA_WIDTH = 512*2**$clog2(PORTS),
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
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parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
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parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Transmit request input (queue index)
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*/
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue,
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input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag,
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input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest,
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input wire s_axis_tx_req_valid,
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output wire s_axis_tx_req_ready,
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/*
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* Transmit request status output
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*/
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output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
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output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag,
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output wire m_axis_tx_req_status_valid,
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/*
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* Descriptor request output
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*/
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
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output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
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output wire m_axis_desc_req_valid,
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input wire m_axis_desc_req_ready,
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/*
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* Descriptor request status input
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*/
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input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
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input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
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input wire [CQN_WIDTH-1:0] s_axis_desc_req_status_cpl,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
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input wire s_axis_desc_req_status_empty,
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input wire s_axis_desc_req_status_error,
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input wire s_axis_desc_req_status_valid,
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/*
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* Descriptor data input
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*/
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input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
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input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
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input wire s_axis_desc_tvalid,
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output wire s_axis_desc_tready,
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input wire s_axis_desc_tlast,
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input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
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input wire s_axis_desc_tuser,
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/*
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* Completion request output
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*/
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output wire [CQN_WIDTH-1:0] m_axis_cpl_req_queue,
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output wire [CPL_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
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output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
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output wire m_axis_cpl_req_valid,
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input wire m_axis_cpl_req_ready,
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/*
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* Completion request status input
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*/
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input wire [CPL_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
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input wire s_axis_cpl_req_status_full,
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input wire s_axis_cpl_req_status_error,
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input wire s_axis_cpl_req_status_valid,
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/*
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* DMA read descriptor output (data)
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
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output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
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output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
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output wire m_axis_dma_read_desc_valid,
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input wire m_axis_dma_read_desc_ready,
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/*
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* DMA read descriptor status input (data)
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*/
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input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
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input wire [3:0] s_axis_dma_read_desc_status_error,
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input wire s_axis_dma_read_desc_status_valid,
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/*
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* RAM interface (data)
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*/
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input wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
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input wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
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input wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
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input wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
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output wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
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output wire [RAM_SEG_COUNT-1:0] dma_ram_wr_done,
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/*
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* Transmit data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
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output wire m_axis_tx_tvalid,
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input wire m_axis_tx_tready,
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output wire m_axis_tx_tlast,
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output wire [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_tid,
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output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_tdest,
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output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
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/*
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* Transmit completion input
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*/
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input wire [PTP_TS_WIDTH-1:0] s_axis_tx_cpl_ts,
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input wire [TX_TAG_WIDTH-1:0] s_axis_tx_cpl_tag,
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input wire s_axis_tx_cpl_valid,
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output wire s_axis_tx_cpl_ready,
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/*
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* Configuration
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*/
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input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
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);
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parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE);
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parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
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wire [AXIS_DESC_DATA_WIDTH-1:0] tx_fifo_desc_tdata;
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wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_fifo_desc_tkeep;
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wire tx_fifo_desc_tvalid;
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wire tx_fifo_desc_tready;
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wire tx_fifo_desc_tlast;
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wire [DESC_REQ_TAG_WIDTH-1:0] tx_fifo_desc_tid;
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wire tx_fifo_desc_tuser;
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axis_fifo #(
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.DEPTH(TX_DESC_FIFO_SIZE*DESC_SIZE),
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.DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
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.KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
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.LAST_ENABLE(1),
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.ID_ENABLE(1),
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.ID_WIDTH(DESC_REQ_TAG_WIDTH),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.RAM_PIPELINE(2),
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.FRAME_FIFO(0)
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)
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tx_desc_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(s_axis_desc_tdata),
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.s_axis_tkeep(s_axis_desc_tkeep),
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.s_axis_tvalid(s_axis_desc_tvalid),
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.s_axis_tready(s_axis_desc_tready),
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.s_axis_tlast(s_axis_desc_tlast),
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.s_axis_tid(s_axis_desc_tid),
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.s_axis_tdest(0),
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.s_axis_tuser(s_axis_desc_tuser),
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// AXI output
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.m_axis_tdata(tx_fifo_desc_tdata),
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.m_axis_tkeep(tx_fifo_desc_tkeep),
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.m_axis_tvalid(tx_fifo_desc_tvalid),
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.m_axis_tready(tx_fifo_desc_tready),
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.m_axis_tlast(tx_fifo_desc_tlast),
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.m_axis_tid(tx_fifo_desc_tid),
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.m_axis_tdest(),
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.m_axis_tuser(tx_fifo_desc_tuser),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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wire tx_csum_cmd_csum_enable;
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wire [7:0] tx_csum_cmd_csum_start;
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wire [7:0] tx_csum_cmd_csum_offset;
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wire tx_csum_cmd_valid;
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wire tx_csum_cmd_ready;
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wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr;
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wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len;
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wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag;
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wire [AXIS_TX_ID_WIDTH-1:0] dma_tx_desc_id;
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wire [AXIS_TX_DEST_WIDTH-1:0] dma_tx_desc_dest;
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wire [AXIS_TX_USER_WIDTH-1:0] dma_tx_desc_user;
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wire dma_tx_desc_valid;
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wire dma_tx_desc_ready;
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wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
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wire [3:0] dma_tx_desc_status_error;
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wire dma_tx_desc_status_valid;
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tx_engine #(
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
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.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
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.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
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.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
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.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
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.CPL_REQ_TAG_WIDTH(CPL_REQ_TAG_WIDTH),
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.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
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.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
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.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
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.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
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.CQN_WIDTH(CQN_WIDTH),
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.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
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.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
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.MAX_TX_SIZE(MAX_TX_SIZE),
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.TX_BUFFER_OFFSET(0),
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.TX_BUFFER_SIZE(TX_RAM_SIZE),
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.TX_BUFFER_STEP_SIZE(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
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.DESC_SIZE(DESC_SIZE),
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.CPL_SIZE(CPL_SIZE),
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.MAX_DESC_REQ(TX_MAX_DESC_REQ),
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.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
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.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),
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.PTP_TS_WIDTH(PTP_TS_WIDTH),
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.TX_TAG_WIDTH(TX_TAG_WIDTH),
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.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
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.AXIS_TX_ID_WIDTH(AXIS_TX_ID_WIDTH),
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.AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
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.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH)
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)
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tx_engine_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Transmit request input (queue index)
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*/
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.s_axis_tx_req_queue(s_axis_tx_req_queue),
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.s_axis_tx_req_tag(s_axis_tx_req_tag),
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.s_axis_tx_req_dest(s_axis_tx_req_dest),
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.s_axis_tx_req_valid(s_axis_tx_req_valid),
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.s_axis_tx_req_ready(s_axis_tx_req_ready),
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/*
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* Transmit request status output
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*/
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.m_axis_tx_req_status_len(m_axis_tx_req_status_len),
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.m_axis_tx_req_status_tag(m_axis_tx_req_status_tag),
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.m_axis_tx_req_status_valid(m_axis_tx_req_status_valid),
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/*
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* Descriptor request output
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*/
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.m_axis_desc_req_queue(m_axis_desc_req_queue),
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.m_axis_desc_req_tag(m_axis_desc_req_tag),
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.m_axis_desc_req_valid(m_axis_desc_req_valid),
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.m_axis_desc_req_ready(m_axis_desc_req_ready),
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/*
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* Descriptor request status input
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*/
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.s_axis_desc_req_status_queue(s_axis_desc_req_status_queue),
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.s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr),
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.s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl),
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.s_axis_desc_req_status_tag(s_axis_desc_req_status_tag),
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.s_axis_desc_req_status_empty(s_axis_desc_req_status_empty),
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.s_axis_desc_req_status_error(s_axis_desc_req_status_error),
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.s_axis_desc_req_status_valid(s_axis_desc_req_status_valid),
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/*
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* Descriptor data input
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*/
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.s_axis_desc_tdata(tx_fifo_desc_tdata),
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.s_axis_desc_tkeep(tx_fifo_desc_tkeep),
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.s_axis_desc_tvalid(tx_fifo_desc_tvalid),
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.s_axis_desc_tready(tx_fifo_desc_tready),
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.s_axis_desc_tlast(tx_fifo_desc_tlast),
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.s_axis_desc_tid(tx_fifo_desc_tid),
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.s_axis_desc_tuser(tx_fifo_desc_tuser),
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/*
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* Completion request output
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*/
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.m_axis_cpl_req_queue(m_axis_cpl_req_queue),
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.m_axis_cpl_req_tag(m_axis_cpl_req_tag),
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.m_axis_cpl_req_data(m_axis_cpl_req_data),
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.m_axis_cpl_req_valid(m_axis_cpl_req_valid),
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.m_axis_cpl_req_ready(m_axis_cpl_req_ready),
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/*
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* Completion request status input
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*/
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.s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag),
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.s_axis_cpl_req_status_full(s_axis_cpl_req_status_full),
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.s_axis_cpl_req_status_error(s_axis_cpl_req_status_error),
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.s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid),
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/*
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* DMA read descriptor output
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*/
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.m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr),
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.m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr),
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.m_axis_dma_read_desc_len(m_axis_dma_read_desc_len),
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.m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag),
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.m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid),
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.m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready),
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/*
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* DMA read descriptor status input
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*/
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.s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag),
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.s_axis_dma_read_desc_status_error(s_axis_dma_read_desc_status_error),
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.s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid),
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/*
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* Transmit descriptor output
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*/
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.m_axis_tx_desc_addr(dma_tx_desc_addr),
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.m_axis_tx_desc_len(dma_tx_desc_len),
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.m_axis_tx_desc_tag(dma_tx_desc_tag),
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.m_axis_tx_desc_id(dma_tx_desc_id),
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.m_axis_tx_desc_dest(dma_tx_desc_dest),
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.m_axis_tx_desc_user(dma_tx_desc_user),
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.m_axis_tx_desc_valid(dma_tx_desc_valid),
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.m_axis_tx_desc_ready(dma_tx_desc_ready),
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/*
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* Transmit descriptor status input
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*/
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.s_axis_tx_desc_status_tag(dma_tx_desc_status_tag),
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.s_axis_tx_desc_status_error(dma_tx_desc_status_error),
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.s_axis_tx_desc_status_valid(dma_tx_desc_status_valid),
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/*
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* Transmit checksum command output
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*/
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.m_axis_tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable),
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.m_axis_tx_csum_cmd_csum_start(tx_csum_cmd_csum_start),
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.m_axis_tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset),
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.m_axis_tx_csum_cmd_valid(tx_csum_cmd_valid),
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.m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready),
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/*
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* Transmit completion input
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*/
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.s_axis_tx_cpl_ts(s_axis_tx_cpl_ts),
|
|
.s_axis_tx_cpl_tag(s_axis_tx_cpl_tag),
|
|
.s_axis_tx_cpl_valid(s_axis_tx_cpl_valid),
|
|
.s_axis_tx_cpl_ready(s_axis_tx_cpl_ready),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(1'b1)
|
|
);
|
|
|
|
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
|
|
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
|
|
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
|
|
|
|
dma_psdpram #(
|
|
.SIZE(TX_RAM_SIZE),
|
|
.SEG_COUNT(RAM_SEG_COUNT),
|
|
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
|
|
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
|
|
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
|
|
.PIPELINE(RAM_PIPELINE)
|
|
)
|
|
dma_psdpram_tx_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Write port
|
|
*/
|
|
.wr_cmd_be(dma_ram_wr_cmd_be),
|
|
.wr_cmd_addr(dma_ram_wr_cmd_addr),
|
|
.wr_cmd_data(dma_ram_wr_cmd_data),
|
|
.wr_cmd_valid(dma_ram_wr_cmd_valid),
|
|
.wr_cmd_ready(dma_ram_wr_cmd_ready),
|
|
.wr_done(dma_ram_wr_done),
|
|
|
|
/*
|
|
* Read port
|
|
*/
|
|
.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
|
|
.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
|
|
.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
|
|
.rd_resp_data(dma_ram_rd_resp_data_int),
|
|
.rd_resp_valid(dma_ram_rd_resp_valid_int),
|
|
.rd_resp_ready(dma_ram_rd_resp_ready_int)
|
|
);
|
|
|
|
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
|
|
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
|
|
wire tx_axis_tvalid_int;
|
|
wire tx_axis_tready_int;
|
|
wire tx_axis_tlast_int;
|
|
wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid_int;
|
|
wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest_int;
|
|
wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser_int;
|
|
|
|
dma_client_axis_source #(
|
|
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
|
|
.SEG_COUNT(RAM_SEG_COUNT),
|
|
.SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
|
|
.SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
|
|
.SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_LAST_ENABLE(1),
|
|
.AXIS_ID_ENABLE(1),
|
|
.AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH),
|
|
.AXIS_DEST_ENABLE(1),
|
|
.AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
|
|
.AXIS_USER_ENABLE(1),
|
|
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH),
|
|
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
|
|
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
|
|
)
|
|
dma_client_axis_source_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* DMA read descriptor input
|
|
*/
|
|
.s_axis_read_desc_ram_addr(dma_tx_desc_addr),
|
|
.s_axis_read_desc_len(dma_tx_desc_len),
|
|
.s_axis_read_desc_tag(dma_tx_desc_tag),
|
|
.s_axis_read_desc_id(dma_tx_desc_id),
|
|
.s_axis_read_desc_dest(dma_tx_desc_dest),
|
|
.s_axis_read_desc_user(dma_tx_desc_user),
|
|
.s_axis_read_desc_valid(dma_tx_desc_valid),
|
|
.s_axis_read_desc_ready(dma_tx_desc_ready),
|
|
|
|
/*
|
|
* DMA read descriptor status output
|
|
*/
|
|
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
|
|
.m_axis_read_desc_status_error(dma_tx_desc_status_error),
|
|
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
|
|
|
|
/*
|
|
* AXI stream read data output
|
|
*/
|
|
.m_axis_read_data_tdata(tx_axis_tdata_int),
|
|
.m_axis_read_data_tkeep(tx_axis_tkeep_int),
|
|
.m_axis_read_data_tvalid(tx_axis_tvalid_int),
|
|
.m_axis_read_data_tready(tx_axis_tready_int),
|
|
.m_axis_read_data_tlast(tx_axis_tlast_int),
|
|
.m_axis_read_data_tid(tx_axis_tid_int),
|
|
.m_axis_read_data_tdest(tx_axis_tdest_int),
|
|
.m_axis_read_data_tuser(tx_axis_tuser_int),
|
|
|
|
/*
|
|
* RAM interface
|
|
*/
|
|
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int),
|
|
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int),
|
|
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int),
|
|
.ram_rd_resp_data(dma_ram_rd_resp_data_int),
|
|
.ram_rd_resp_valid(dma_ram_rd_resp_valid_int),
|
|
.ram_rd_resp_ready(dma_ram_rd_resp_ready_int),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.enable(1'b1)
|
|
);
|
|
|
|
mqnic_egress #(
|
|
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
|
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
|
|
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
|
.AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH),
|
|
.AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
|
|
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH),
|
|
.MAX_TX_SIZE(MAX_TX_SIZE)
|
|
)
|
|
egress_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
|
|
/*
|
|
* Transmit data input
|
|
*/
|
|
.s_axis_tdata(tx_axis_tdata_int),
|
|
.s_axis_tkeep(tx_axis_tkeep_int),
|
|
.s_axis_tvalid(tx_axis_tvalid_int),
|
|
.s_axis_tready(tx_axis_tready_int),
|
|
.s_axis_tlast(tx_axis_tlast_int),
|
|
.s_axis_tid(tx_axis_tid_int),
|
|
.s_axis_tdest(tx_axis_tdest_int),
|
|
.s_axis_tuser(tx_axis_tuser_int),
|
|
|
|
/*
|
|
* Transmit data output
|
|
*/
|
|
.m_axis_tdata(m_axis_tx_tdata),
|
|
.m_axis_tkeep(m_axis_tx_tkeep),
|
|
.m_axis_tvalid(m_axis_tx_tvalid),
|
|
.m_axis_tready(m_axis_tx_tready),
|
|
.m_axis_tlast(m_axis_tx_tlast),
|
|
.m_axis_tid(m_axis_tx_tid),
|
|
.m_axis_tdest(m_axis_tx_tdest),
|
|
.m_axis_tuser(m_axis_tx_tuser),
|
|
|
|
/*
|
|
* Transmit checksum command
|
|
*/
|
|
.tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable),
|
|
.tx_csum_cmd_csum_start(tx_csum_cmd_csum_start),
|
|
.tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset),
|
|
.tx_csum_cmd_valid(tx_csum_cmd_valid),
|
|
.tx_csum_cmd_ready(tx_csum_cmd_ready)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|