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212 lines
7.6 KiB
Verilog
212 lines
7.6 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2021-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PTP period output
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*/
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module mqnic_ptp_perout #
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(
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parameter REG_ADDR_WIDTH = 6,
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
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input wire reg_wr_en,
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output wire reg_wr_wait,
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output wire reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
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input wire reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
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output wire reg_rd_wait,
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output wire reg_rd_ack,
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/*
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* PTP clock
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*/
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input wire [95:0] ptp_ts_96,
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input wire ptp_ts_step,
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output wire ptp_perout_locked,
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output wire ptp_perout_error,
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output wire ptp_perout_pulse
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);
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localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
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// check configuration
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initial begin
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if (REG_DATA_WIDTH != 32) begin
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$error("Error: Register interface width must be 32 (instance %m)");
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$finish;
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end
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if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
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$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (REG_ADDR_WIDTH < 6) begin
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$error("Error: Register address width too narrow (instance %m)");
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$finish;
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end
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if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 7'h40) begin
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$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
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$finish;
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end
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end
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reg ptp_perout_enable_reg = 1'b0;
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// control registers
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reg reg_wr_ack_reg = 1'b0;
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reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
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reg reg_rd_ack_reg = 1'b0;
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reg [95:0] set_ptp_perout_start_reg = 0;
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reg set_ptp_perout_start_valid_reg = 0;
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reg [95:0] set_ptp_perout_period_reg = 0;
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reg set_ptp_perout_period_valid_reg = 0;
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reg [95:0] set_ptp_perout_width_reg = 0;
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reg set_ptp_perout_width_valid_reg = 0;
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assign reg_wr_wait = 1'b0;
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assign reg_wr_ack = reg_wr_ack_reg;
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assign reg_rd_data = reg_rd_data_reg;
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assign reg_rd_wait = 1'b0;
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assign reg_rd_ack = reg_rd_ack_reg;
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always @(posedge clk) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_data_reg <= 0;
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reg_rd_ack_reg <= 1'b0;
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set_ptp_perout_start_valid_reg <= 1'b0;
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set_ptp_perout_period_valid_reg <= 1'b0;
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set_ptp_perout_width_valid_reg <= 1'b0;
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if (reg_wr_en && !reg_wr_ack_reg) begin
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// write operation
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reg_wr_ack_reg <= 1'b1;
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case ({reg_wr_addr >> 2, 2'b00})
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RBB+6'h0C: begin
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// PTP perout control and status
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ptp_perout_enable_reg <= reg_wr_data[0];
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end
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RBB+6'h10: set_ptp_perout_start_reg[15:0] <= reg_wr_data; // PTP perout start fns
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RBB+6'h14: set_ptp_perout_start_reg[45:16] <= reg_wr_data; // PTP perout start ns
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RBB+6'h18: set_ptp_perout_start_reg[79:48] <= reg_wr_data; // PTP perout start sec l
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RBB+6'h1C: begin
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// PTP perout start sec h
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set_ptp_perout_start_reg[95:80] <= reg_wr_data;
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set_ptp_perout_start_valid_reg <= 1'b1;
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end
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RBB+6'h20: set_ptp_perout_period_reg[15:0] <= reg_wr_data; // PTP perout period fns
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RBB+6'h24: set_ptp_perout_period_reg[45:16] <= reg_wr_data; // PTP perout period ns
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RBB+6'h28: set_ptp_perout_period_reg[79:48] <= reg_wr_data; // PTP perout period sec l
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RBB+6'h2C: begin
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// PTP perout period sec h
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set_ptp_perout_period_reg[95:80] <= reg_wr_data;
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set_ptp_perout_period_valid_reg <= 1'b1;
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end
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RBB+6'h30: set_ptp_perout_width_reg[15:0] <= reg_wr_data; // PTP perout width fns
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RBB+6'h34: set_ptp_perout_width_reg[45:16] <= reg_wr_data; // PTP perout width ns
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RBB+6'h38: set_ptp_perout_width_reg[79:48] <= reg_wr_data; // PTP perout width sec l
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RBB+6'h3C: begin
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// PTP perout width sec h
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set_ptp_perout_width_reg[95:80] <= reg_wr_data;
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set_ptp_perout_width_valid_reg <= 1'b1;
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end
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default: reg_wr_ack_reg <= 1'b0;
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endcase
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end
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if (reg_rd_en && !reg_rd_ack_reg) begin
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// read operation
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reg_rd_ack_reg <= 1'b1;
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case ({reg_rd_addr >> 2, 2'b00})
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RBB+6'h00: reg_rd_data_reg <= 32'h0000C081; // PHC: Type
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RBB+6'h04: reg_rd_data_reg <= 32'h00000100; // PHC: Version
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RBB+6'h08: reg_rd_data_reg <= RB_NEXT_PTR; // PHC: Next header
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RBB+6'h0C: begin
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// PTP perout control and status
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reg_rd_data_reg[0] <= ptp_perout_enable_reg;
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reg_rd_data_reg[8] <= ptp_perout_pulse;
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reg_rd_data_reg[16] <= ptp_perout_locked;
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reg_rd_data_reg[24] <= ptp_perout_error;
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end
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RBB+6'h10: reg_rd_data_reg <= set_ptp_perout_start_reg[15:0]; // PTP perout start fns
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RBB+6'h14: reg_rd_data_reg <= set_ptp_perout_start_reg[45:16]; // PTP perout start ns
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RBB+6'h18: reg_rd_data_reg <= set_ptp_perout_start_reg[79:48]; // PTP perout start sec l
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RBB+6'h1C: reg_rd_data_reg <= set_ptp_perout_start_reg[95:80]; // PTP perout start sec h
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RBB+6'h20: reg_rd_data_reg <= set_ptp_perout_period_reg[15:0]; // PTP perout period fns
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RBB+6'h24: reg_rd_data_reg <= set_ptp_perout_period_reg[45:16]; // PTP perout period ns
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RBB+6'h28: reg_rd_data_reg <= set_ptp_perout_period_reg[79:48]; // PTP perout period sec l
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RBB+6'h2C: reg_rd_data_reg <= set_ptp_perout_period_reg[95:80]; // PTP perout period sec h
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RBB+6'h30: reg_rd_data_reg <= set_ptp_perout_width_reg[15:0]; // PTP perout width fns
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RBB+6'h34: reg_rd_data_reg <= set_ptp_perout_width_reg[45:16]; // PTP perout width ns
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RBB+6'h38: reg_rd_data_reg <= set_ptp_perout_width_reg[79:48]; // PTP perout width sec l
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RBB+6'h3C: reg_rd_data_reg <= set_ptp_perout_width_reg[95:80]; // PTP perout width sec h
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default: reg_rd_ack_reg <= 1'b0;
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endcase
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end
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if (rst) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_ack_reg <= 1'b0;
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ptp_perout_enable_reg <= 1'b0;
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end
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end
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ptp_perout #(
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.FNS_ENABLE(0),
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.OUT_START_S(0),
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.OUT_START_NS(0),
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.OUT_START_FNS(0),
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.OUT_PERIOD_S(1),
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.OUT_PERIOD_NS(0),
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.OUT_PERIOD_FNS(0),
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.OUT_WIDTH_S(0),
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.OUT_WIDTH_NS(500000000),
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.OUT_WIDTH_FNS(0)
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)
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ptp_perout_inst (
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.clk(clk),
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.rst(rst),
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.input_ts_96(ptp_ts_96),
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.input_ts_step(ptp_ts_step),
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.enable(ptp_perout_enable_reg),
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.input_start(set_ptp_perout_start_reg),
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.input_start_valid(set_ptp_perout_start_valid_reg),
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.input_period(set_ptp_perout_period_reg),
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.input_period_valid(set_ptp_perout_period_valid_reg),
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.input_width(set_ptp_perout_width_reg),
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.input_width_valid(set_ptp_perout_width_valid_reg),
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.locked(ptp_perout_locked),
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.error(ptp_perout_error),
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.output_pulse(ptp_perout_pulse)
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);
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endmodule
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`resetall
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