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264 lines
7.3 KiB
Verilog
264 lines
7.3 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2022-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* DRP register block
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*/
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module rb_drp #
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(
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parameter DRP_ADDR_WIDTH = 10,
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parameter DRP_DATA_WIDTH = 15,
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parameter DRP_INFO = 32'd0,
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parameter REG_ADDR_WIDTH = 16,
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parameter REG_DATA_WIDTH = 32,
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parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8),
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parameter RB_TYPE = 32'h0000C150,
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parameter RB_BASE_ADDR = 0,
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parameter RB_NEXT_PTR = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Register interface
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*/
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input wire [REG_ADDR_WIDTH-1:0] reg_wr_addr,
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input wire [REG_DATA_WIDTH-1:0] reg_wr_data,
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input wire [REG_STRB_WIDTH-1:0] reg_wr_strb,
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input wire reg_wr_en,
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output wire reg_wr_wait,
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output wire reg_wr_ack,
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input wire [REG_ADDR_WIDTH-1:0] reg_rd_addr,
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input wire reg_rd_en,
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output wire [REG_DATA_WIDTH-1:0] reg_rd_data,
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output wire reg_rd_wait,
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output wire reg_rd_ack,
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/*
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* DRP
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*/
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input wire drp_clk,
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input wire drp_rst,
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output wire [DRP_ADDR_WIDTH-1:0] drp_addr,
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output wire [DRP_DATA_WIDTH-1:0] drp_di,
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output wire drp_en,
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output wire drp_we,
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input wire [DRP_DATA_WIDTH-1:0] drp_do,
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input wire drp_rdy
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);
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localparam RBB = RB_BASE_ADDR & {REG_ADDR_WIDTH{1'b1}};
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// check configuration
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initial begin
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if (REG_DATA_WIDTH != 32) begin
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$error("Error: Register interface width must be 32 (instance %m)");
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$finish;
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end
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if (REG_STRB_WIDTH * 8 != REG_DATA_WIDTH) begin
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$error("Error: Register interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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if (REG_ADDR_WIDTH < 7) begin
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$error("Error: Register address width too narrow (instance %m)");
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$finish;
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end
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if (RB_NEXT_PTR >= RB_BASE_ADDR && RB_NEXT_PTR < RB_BASE_ADDR + 7'h20) begin
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$error("Error: RB_NEXT_PTR overlaps block (instance %m)");
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$finish;
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end
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end
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// control registers
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reg reg_wr_ack_reg = 1'b0;
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reg [REG_DATA_WIDTH-1:0] reg_rd_data_reg = 0;
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reg reg_rd_ack_reg = 1'b0;
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reg [1:0] rb_state_reg = 2'd0;
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reg rb_flag_reg = 1'b0;
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(* srl_style = "register" *)
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reg rb_flag_sync_reg_1 = 1'b0;
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(* srl_style = "register" *)
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reg rb_flag_sync_reg_2 = 1'b0;
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reg [1:0] drp_state_reg = 2'd0;
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reg drp_flag_reg = 1'b0;
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(* srl_style = "register" *)
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reg drp_flag_sync_reg_1 = 1'b0;
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(* srl_style = "register" *)
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reg drp_flag_sync_reg_2 = 1'b0;
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reg [DRP_ADDR_WIDTH-1:0] rb_ctrl_addr_reg = 0;
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reg [DRP_DATA_WIDTH-1:0] rb_ctrl_di_reg = 0;
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reg rb_ctrl_we_reg = 1'b0;
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reg rb_ctrl_en_reg = 1'b0;
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reg [DRP_ADDR_WIDTH-1:0] rb_addr_reg = 0;
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reg [DRP_DATA_WIDTH-1:0] rb_di_reg = 0;
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reg [DRP_DATA_WIDTH-1:0] rb_do_reg = 0;
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reg rb_we_reg = 1'b0;
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reg [DRP_ADDR_WIDTH-1:0] drp_addr_reg = 0;
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reg [DRP_DATA_WIDTH-1:0] drp_di_reg = 0;
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reg [DRP_DATA_WIDTH-1:0] drp_do_reg = 0;
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reg drp_en_reg = 1'b0;
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reg drp_we_reg = 1'b0;
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reg drp_do_valid_reg = 1'b0;
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assign reg_wr_wait = 1'b0;
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assign reg_wr_ack = reg_wr_ack_reg;
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assign reg_rd_data = reg_rd_data_reg;
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assign reg_rd_wait = 1'b0;
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assign reg_rd_ack = reg_rd_ack_reg;
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assign drp_addr = drp_addr_reg;
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assign drp_di = drp_di_reg;
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assign drp_en = drp_en_reg;
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assign drp_we = drp_we_reg;
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always @(posedge drp_clk) begin
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drp_en_reg <= 1'b0;
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drp_we_reg <= 1'b0;
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if (drp_rdy) begin
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drp_do_reg <= drp_do;
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drp_do_valid_reg <= 1'b1;
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end
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case (drp_state_reg)
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2'd0: begin
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if (rb_flag_sync_reg_2) begin
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drp_state_reg <= 2'd1;
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drp_addr_reg <= rb_addr_reg;
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drp_di_reg <= rb_di_reg;
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drp_en_reg <= 1'b1;
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drp_we_reg <= rb_we_reg;
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drp_do_valid_reg <= 1'b0;
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end
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end
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2'd1: begin
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if (drp_do_valid_reg) begin
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drp_state_reg <= 2'd2;
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drp_flag_reg <= 1'b1;
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end
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end
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2'd2: begin
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if (!rb_flag_sync_reg_2) begin
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drp_state_reg <= 2'd0;
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drp_flag_reg <= 1'b0;
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end
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end
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endcase
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if (drp_rst) begin
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drp_state_reg <= 2'd0;
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drp_flag_reg <= 1'b0;
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drp_en_reg <= 1'b0;
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drp_we_reg <= 1'b0;
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drp_do_valid_reg <= 1'b0;
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end
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end
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// synchronization
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always @(posedge clk) begin
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drp_flag_sync_reg_1 <= drp_flag_reg;
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drp_flag_sync_reg_2 <= drp_flag_sync_reg_1;
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end
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always @(posedge drp_clk) begin
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rb_flag_sync_reg_1 <= rb_flag_reg;
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rb_flag_sync_reg_2 <= rb_flag_sync_reg_1;
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end
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always @(posedge clk) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_data_reg <= 0;
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reg_rd_ack_reg <= 1'b0;
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case (rb_state_reg)
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2'd0: begin
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if (rb_ctrl_en_reg) begin
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rb_state_reg <= 2'd1;
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rb_flag_reg <= 1'b1;
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rb_addr_reg <= rb_ctrl_addr_reg;
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rb_di_reg <= rb_ctrl_di_reg;
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rb_we_reg <= rb_ctrl_we_reg;
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end
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end
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2'd1: begin
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if (drp_flag_sync_reg_2) begin
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rb_state_reg <= 2'd2;
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rb_flag_reg <= 1'b0;
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rb_do_reg <= drp_do_reg;
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end
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end
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2'd2: begin
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if (!drp_flag_sync_reg_2) begin
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rb_state_reg <= 2'd0;
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rb_ctrl_en_reg <= 1'b0;
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end
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end
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endcase
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if (reg_wr_en && !reg_wr_ack_reg) begin
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// write operation
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reg_wr_ack_reg <= 1'b1;
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case ({reg_wr_addr >> 2, 2'b00})
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RBB+7'h10: begin
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// DRP: control
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rb_ctrl_en_reg <= reg_wr_data[0];
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rb_ctrl_we_reg <= reg_wr_data[1];
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end
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RBB+7'h14: rb_ctrl_addr_reg <= reg_wr_data; // DRP: address
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RBB+7'h18: rb_ctrl_di_reg <= reg_wr_data; // DRP: data in
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default: reg_wr_ack_reg <= 1'b0;
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endcase
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end
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if (reg_rd_en && !reg_rd_ack_reg) begin
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// read operation
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reg_rd_ack_reg <= 1'b1;
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case ({reg_rd_addr >> 2, 2'b00})
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RBB+7'h00: reg_rd_data_reg <= RB_TYPE; // DRP: Type
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RBB+7'h04: reg_rd_data_reg <= 32'h00000100; // DRP: Version
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RBB+7'h08: reg_rd_data_reg <= RB_NEXT_PTR; // DRP: Next header
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RBB+7'h0C: reg_rd_data_reg <= DRP_INFO; // DRP: info
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RBB+7'h10: begin
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// DRP: control
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reg_rd_data_reg[0] <= rb_ctrl_en_reg;
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reg_rd_data_reg[1] <= rb_ctrl_we_reg;
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reg_rd_data_reg[8] <= (rb_state_reg != 2'd0);
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end
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RBB+7'h14: reg_rd_data_reg <= rb_ctrl_addr_reg; // DRP: address
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RBB+7'h18: reg_rd_data_reg <= rb_ctrl_di_reg; // DRP: data in
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RBB+7'h1C: reg_rd_data_reg <= rb_do_reg; // DRP: data out
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default: reg_rd_ack_reg <= 1'b0;
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endcase
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end
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if (rst) begin
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reg_wr_ack_reg <= 1'b0;
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reg_rd_ack_reg <= 1'b0;
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rb_state_reg <= 2'd0;
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rb_ctrl_en_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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