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232 lines
7.3 KiB
Verilog
232 lines
7.3 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2021-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* RX FIFO
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*/
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module rx_fifo #
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(
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// FIFO depth in words (each FIFO)
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// KEEP_WIDTH words per cycle if KEEP_ENABLE set
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// Rounded up to nearest power of 2 cycles
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parameter FIFO_DEPTH = 4096,
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// Width of FIFO depth status signals
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parameter FIFO_DEPTH_WIDTH = $clog2(FIFO_DEPTH)+1,
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// Number of AXI stream inputs
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parameter PORTS = 4,
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// Width of input AXI stream interfaces in bits
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parameter S_DATA_WIDTH = 8,
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// Propagate tkeep signal
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parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
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// Width of output AXI stream interface in bits
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parameter M_DATA_WIDTH = 8*PORTS,
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// Propagate tkeep signal
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parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
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// tkeep signal width (words per cycle)
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parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
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// Propagate tid signal
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parameter ID_ENABLE = 1,
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// input tid signal width
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parameter S_ID_WIDTH = 1,
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// output tid signal width
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parameter M_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
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// Propagate tdest signal
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parameter DEST_ENABLE = 0,
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// tdest signal width
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parameter DEST_WIDTH = 8,
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// Propagate tuser signal
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parameter USER_ENABLE = 1,
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// tuser signal width
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parameter USER_WIDTH = 1,
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// number of RAM pipeline registers
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parameter RAM_PIPELINE = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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input wire [PORTS*S_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [PORTS*S_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire [PORTS-1:0] s_axis_tvalid,
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output wire [PORTS-1:0] s_axis_tready,
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input wire [PORTS-1:0] s_axis_tlast,
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input wire [PORTS*S_ID_WIDTH-1:0] s_axis_tid,
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input wire [PORTS*DEST_WIDTH-1:0] s_axis_tdest,
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input wire [PORTS*USER_WIDTH-1:0] s_axis_tuser,
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/*
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* AXI Stream output
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*/
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output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [M_ID_WIDTH-1:0] m_axis_tid,
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output wire [DEST_WIDTH-1:0] m_axis_tdest,
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output wire [USER_WIDTH-1:0] m_axis_tuser,
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/*
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* Status
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*/
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output wire [FIFO_DEPTH_WIDTH*PORTS-1:0] status_depth,
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output wire [FIFO_DEPTH_WIDTH*PORTS-1:0] status_depth_commit,
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output wire [PORTS-1:0] status_overflow,
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output wire [PORTS-1:0] status_bad_frame,
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output wire [PORTS-1:0] status_good_frame
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);
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wire [PORTS*M_DATA_WIDTH-1:0] axis_fifo_tdata;
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wire [PORTS*M_KEEP_WIDTH-1:0] axis_fifo_tkeep;
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wire [PORTS-1:0] axis_fifo_tvalid;
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wire [PORTS-1:0] axis_fifo_tready;
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wire [PORTS-1:0] axis_fifo_tlast;
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wire [PORTS*S_ID_WIDTH-1:0] axis_fifo_tid;
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wire [PORTS*DEST_WIDTH-1:0] axis_fifo_tdest;
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wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser;
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generate
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genvar n;
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for (n = 0; n < PORTS; n = n + 1) begin : fifo
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axis_fifo_adapter #(
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.DEPTH(FIFO_DEPTH),
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.S_DATA_WIDTH(S_DATA_WIDTH),
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.S_KEEP_ENABLE(S_KEEP_ENABLE),
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.S_KEEP_WIDTH(S_KEEP_WIDTH),
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.M_DATA_WIDTH(M_DATA_WIDTH),
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.M_KEEP_ENABLE(M_KEEP_ENABLE),
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.M_KEEP_WIDTH(M_KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.ID_WIDTH(S_ID_WIDTH),
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.DEST_ENABLE(DEST_ENABLE),
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.DEST_WIDTH(DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH),
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.RAM_PIPELINE(RAM_PIPELINE),
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.FRAME_FIFO(1),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(1),
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.DROP_BAD_FRAME(USER_ENABLE),
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.DROP_WHEN_FULL(0),
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.MARK_WHEN_FULL(0),
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.PAUSE_ENABLE(0),
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.FRAME_PAUSE(1)
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)
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fifo_inst (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(s_axis_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]),
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.s_axis_tkeep(s_axis_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]),
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.s_axis_tvalid(s_axis_tvalid[n +: 1]),
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.s_axis_tready(s_axis_tready[n +: 1]),
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.s_axis_tlast(s_axis_tlast[n +: 1]),
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.s_axis_tid(s_axis_tid[n*S_ID_WIDTH +: S_ID_WIDTH]),
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.s_axis_tdest(s_axis_tdest[n*DEST_WIDTH +: DEST_WIDTH]),
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.s_axis_tuser(s_axis_tuser[n*USER_WIDTH +: USER_WIDTH]),
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// AXI output
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.m_axis_tdata(axis_fifo_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]),
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.m_axis_tkeep(axis_fifo_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]),
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.m_axis_tvalid(axis_fifo_tvalid[n +: 1]),
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.m_axis_tready(axis_fifo_tready[n +: 1]),
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.m_axis_tlast(axis_fifo_tlast[n +: 1]),
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.m_axis_tid(axis_fifo_tid[n*S_ID_WIDTH +: S_ID_WIDTH]),
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.m_axis_tdest(axis_fifo_tdest[n*DEST_WIDTH +: DEST_WIDTH]),
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.m_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]),
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// Pause
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.pause_req(1'b0),
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.pause_ack(),
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// Status
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.status_depth(status_depth[n*FIFO_DEPTH_WIDTH +: FIFO_DEPTH_WIDTH]),
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.status_depth_commit(status_depth_commit[n*FIFO_DEPTH_WIDTH +: FIFO_DEPTH_WIDTH]),
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.status_overflow(status_overflow[n]),
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.status_bad_frame(status_bad_frame[n]),
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.status_good_frame(status_good_frame[n])
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);
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end
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if (PORTS > 1) begin : mux
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axis_arb_mux #(
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.S_COUNT(PORTS),
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.DATA_WIDTH(M_DATA_WIDTH),
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.KEEP_ENABLE(M_KEEP_ENABLE),
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.KEEP_WIDTH(M_KEEP_WIDTH),
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.ID_ENABLE(ID_ENABLE),
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.S_ID_WIDTH(S_ID_WIDTH),
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.M_ID_WIDTH(M_ID_WIDTH),
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.DEST_ENABLE(DEST_ENABLE),
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.DEST_WIDTH(DEST_WIDTH),
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.USER_ENABLE(USER_ENABLE),
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.USER_WIDTH(USER_WIDTH),
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.LAST_ENABLE(1'b1),
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.UPDATE_TID(1),
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.ARB_TYPE_ROUND_ROBIN(1'b1),
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.ARB_LSB_HIGH_PRIORITY(1'b1)
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)
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mux_inst (
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.clk(clk),
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.rst(rst),
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// AXI Stream inputs
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.s_axis_tdata(axis_fifo_tdata),
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.s_axis_tkeep(axis_fifo_tkeep),
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.s_axis_tvalid(axis_fifo_tvalid),
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.s_axis_tready(axis_fifo_tready),
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.s_axis_tlast(axis_fifo_tlast),
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.s_axis_tid(axis_fifo_tid),
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.s_axis_tdest(axis_fifo_tdest),
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.s_axis_tuser(axis_fifo_tuser),
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// AXI Stream output
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tkeep(m_axis_tkeep),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tid(m_axis_tid),
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.m_axis_tdest(m_axis_tdest),
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.m_axis_tuser(m_axis_tuser)
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);
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end else begin
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assign m_axis_tdata = axis_fifo_tdata;
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assign m_axis_tkeep = axis_fifo_tkeep;
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assign m_axis_tvalid = axis_fifo_tvalid;
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assign axis_fifo_tready = m_axis_tready;
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assign m_axis_tlast = axis_fifo_tlast;
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assign m_axis_tid = axis_fifo_tid;
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assign m_axis_tdest = axis_fifo_tdest;
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assign m_axis_tuser = axis_fifo_tuser;
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end
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endgenerate
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endmodule
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`resetall
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