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207 lines
7.1 KiB
Verilog
207 lines
7.1 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics for PCIe TLP traffic
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*/
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module stats_pcie_tlp #
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(
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP monitor input
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*/
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input wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr,
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input wire [TLP_SEG_COUNT-1:0] tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] tlp_eop,
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/*
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* Statistics outputs
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*/
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output wire stat_tlp_mem_rd,
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output wire stat_tlp_mem_wr,
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output wire stat_tlp_io,
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output wire stat_tlp_cfg,
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output wire stat_tlp_msg,
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output wire stat_tlp_cpl,
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output wire stat_tlp_cpl_ur,
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output wire stat_tlp_cpl_ca,
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output wire stat_tlp_atomic,
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output wire stat_tlp_ep,
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output wire [2:0] stat_tlp_hdr_dw,
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output wire [10:0] stat_tlp_req_dw,
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output wire [10:0] stat_tlp_payload_dw,
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output wire [10:0] stat_tlp_cpl_dw
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);
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localparam [2:0]
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TLP_FMT_3DW = 3'b000,
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TLP_FMT_4DW = 3'b001,
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TLP_FMT_3DW_DATA = 3'b010,
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TLP_FMT_4DW_DATA = 3'b011,
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TLP_FMT_PREFIX = 3'b100;
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localparam [2:0]
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CPL_STATUS_SC = 3'b000, // successful completion
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CPL_STATUS_UR = 3'b001, // unsupported request
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CPL_STATUS_CRS = 3'b010, // configuration request retry status
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CPL_STATUS_CA = 3'b100; // completer abort
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reg [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT-1:0] tlp_valid_reg = 0;
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reg [TLP_SEG_COUNT-1:0] tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] tlp_eop_reg = 0;
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reg stat_tlp_mem_rd_reg = 1'b0;
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reg stat_tlp_mem_wr_reg = 1'b0;
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reg stat_tlp_io_reg = 1'b0;
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reg stat_tlp_cfg_reg = 1'b0;
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reg stat_tlp_msg_reg = 1'b0;
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reg stat_tlp_cpl_reg = 1'b0;
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reg stat_tlp_cpl_ur_reg = 1'b0;
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reg stat_tlp_cpl_ca_reg = 1'b0;
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reg stat_tlp_atomic_reg = 1'b0;
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reg stat_tlp_ep_reg = 1'b0;
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reg [2:0] stat_tlp_hdr_dw_reg = 3'd0;
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reg [10:0] stat_tlp_req_dw_reg = 11'd0;
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reg [10:0] stat_tlp_payload_dw_reg = 11'd0;
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reg [10:0] stat_tlp_cpl_dw_reg = 11'd0;
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wire tlp_hdr_valid = tlp_valid_reg && tlp_sop_reg;
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wire [7:0] tlp_hdr_fmt_type = tlp_hdr_reg[127:120];
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wire [2:0] tlp_hdr_fmt = tlp_hdr_reg[127:125];
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wire [4:0] tlp_hdr_type = tlp_hdr_reg[124:120];
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wire tlp_hdr_ep = tlp_hdr_reg[110];
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wire [9:0] tlp_hdr_length = tlp_hdr_reg[105:96];
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wire [3:0] tlp_hdr_cpl_status = tlp_hdr_reg[79:77];
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assign stat_tlp_mem_rd = stat_tlp_mem_rd_reg;
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assign stat_tlp_mem_wr = stat_tlp_mem_wr_reg;
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assign stat_tlp_io = stat_tlp_io_reg;
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assign stat_tlp_cfg = stat_tlp_cfg_reg;
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assign stat_tlp_msg = stat_tlp_msg_reg;
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assign stat_tlp_cpl = stat_tlp_cpl_reg;
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assign stat_tlp_cpl_ur = stat_tlp_cpl_ur_reg;
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assign stat_tlp_cpl_ca = stat_tlp_cpl_ca_reg;
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assign stat_tlp_atomic = stat_tlp_atomic_reg;
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assign stat_tlp_ep = stat_tlp_ep_reg;
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assign stat_tlp_hdr_dw = stat_tlp_hdr_dw_reg;
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assign stat_tlp_req_dw = stat_tlp_req_dw_reg;
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assign stat_tlp_payload_dw = stat_tlp_payload_dw_reg;
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assign stat_tlp_cpl_dw = stat_tlp_cpl_dw_reg;
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always @(posedge clk) begin
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tlp_hdr_reg <= tlp_hdr;
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tlp_valid_reg <= tlp_valid;
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tlp_sop_reg <= tlp_sop;
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tlp_eop_reg <= tlp_eop;
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stat_tlp_mem_rd_reg <= 1'b0;
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stat_tlp_mem_wr_reg <= 1'b0;
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stat_tlp_io_reg <= 1'b0;
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stat_tlp_cfg_reg <= 1'b0;
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stat_tlp_msg_reg <= 1'b0;
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stat_tlp_cpl_reg <= 1'b0;
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stat_tlp_cpl_ur_reg <= 1'b0;
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stat_tlp_cpl_ca_reg <= 1'b0;
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stat_tlp_atomic_reg <= 1'b0;
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stat_tlp_ep_reg <= 1'b0;
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stat_tlp_hdr_dw_reg <= 0;
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stat_tlp_req_dw_reg <= 0;
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stat_tlp_payload_dw_reg <= 0;
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stat_tlp_cpl_dw_reg <= 0;
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if (tlp_hdr_valid) begin
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casez (tlp_hdr_fmt_type)
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8'b00z_0000z: stat_tlp_mem_rd_reg <= 1'b1;
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8'b01z_00000: stat_tlp_mem_wr_reg <= 1'b1;
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8'b0z0_00010: stat_tlp_io_reg <= 1'b1;
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8'b0z0_0010z: stat_tlp_cfg_reg <= 1'b1;
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8'b0z1_10zzz: stat_tlp_msg_reg <= 1'b1;
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8'b0z0_0101z: begin
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stat_tlp_cpl_reg <= 1'b1;
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stat_tlp_cpl_ur_reg <= tlp_hdr_cpl_status == CPL_STATUS_UR;
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stat_tlp_cpl_ca_reg <= tlp_hdr_cpl_status == CPL_STATUS_CA;
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end
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8'b01z_01100: stat_tlp_atomic_reg <= 1'b1;
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8'b01z_01101: stat_tlp_atomic_reg <= 1'b1;
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8'b01z_01110: stat_tlp_atomic_reg <= 1'b1;
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endcase
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stat_tlp_ep_reg <= tlp_hdr_ep;
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stat_tlp_hdr_dw_reg <= tlp_hdr_fmt[0] ? 3'd4 : 3'd3;
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if (tlp_hdr_fmt[1]) begin
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if (tlp_hdr_type == 5'b01010 || tlp_hdr_type == 5'b01011) begin
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stat_tlp_cpl_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
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end else begin
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stat_tlp_payload_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
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end
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end else begin
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stat_tlp_req_dw_reg <= tlp_hdr_length == 0 ? 11'd1024 : tlp_hdr_length;
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end
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end
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if (rst) begin
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tlp_valid_reg <= 0;
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tlp_sop_reg <= 0;
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tlp_eop_reg <= 0;
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stat_tlp_mem_rd_reg <= 0;
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stat_tlp_mem_wr_reg <= 0;
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stat_tlp_io_reg <= 0;
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stat_tlp_cfg_reg <= 0;
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stat_tlp_msg_reg <= 0;
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stat_tlp_cpl_reg <= 0;
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stat_tlp_cpl_ur_reg <= 0;
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stat_tlp_cpl_ca_reg <= 0;
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stat_tlp_atomic_reg <= 0;
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stat_tlp_ep_reg <= 0;
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stat_tlp_hdr_dw_reg <= 0;
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stat_tlp_req_dw_reg <= 0;
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stat_tlp_payload_dw_reg <= 0;
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stat_tlp_cpl_dw_reg <= 0;
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end
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end
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endmodule
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`resetall
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