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Alex Forencich 7914445ac0 Rename AU200 to Alveo
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-07 22:48:37 -08:00

5 lines
193 B
Tcl

# Timing constraints for FPGA boot logic
set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]