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corundum/fpga/mqnic/DE10_Agilex/fpga_100g
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Alex Forencich ba55a3c1ed fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-28 18:57:10 -08:00
..
common
fpga/mqnic: Update makefile path handling
2023-03-24 00:39:45 -07:00
fpga_10g
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_10g_24AR0
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_25g
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_25g_24AR0
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_100g
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_100g_24AR0
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_100g_app_dma_bench
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
fpga_100g_app_dma_bench_24AR0
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
ip
fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex
2023-11-13 20:49:04 -08:00
rtl
fpga/mqnic: Fix AXIL_CSR_ADDR_WIDTH parameter
2023-11-28 18:57:10 -08:00
tb/fpga_core
fpga/mqnic/DE10_Agilex: Merge 25G into 100G for DE10-Agilex
2023-11-13 20:49:04 -08:00
app
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
fpga.qsf
fpga/mqnic: Clean up IO constraints for Intel devices
2023-11-19 21:15:05 -08:00
fpga.sdc
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
lib
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
mac_25g.sdc
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
mac_100g.sdc
fpga/mqnic/DE10_Agilex: Fix MAC timing constraints for DE10-Agilex
2023-11-14 18:11:59 -08:00
README.md
fpga/mqnic: Clean up readmes
2023-06-26 00:08:49 -07:00

README.md

Corundum mqnic for DE10-Agilex

Introduction

This design targets the Terasic DE10-Agilex FPGA development board.

  • FPGA: AGFB014R24B2E2V
  • PHY: E-Tile

Quick start

Build FPGA bitstream

Run make in the fpga subdirectory to build the bitstream. Ensure that the Intel Quartus Pro toolchain components are in PATH.

Build driver and userspace tools

On the host system, run make in modules/mqnic to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run make in utils to build the userspace tools.

Testing

Run make program to program the board with Quartus. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with insmod mqnic.ko. Check dmesg for output from driver initialization, and run mqnic-dump -d /dev/mqnic0 to dump the internal state.