Alex Forencich 009a80aff2 Add completion write module

2019-09-23 14:44:08 -07:00

..

cpl_queue_manager.v

Fix pipelining bug

2019-09-13 13:48:48 -07:00

cpl_write.v

Add completion write module

2019-09-23 14:44:08 -07:00

desc_fetch.v

Add descriptor fetch module

2019-09-23 14:41:35 -07:00

event_mux.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

event_queue.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

interface.v

Increase crossbar threads count

2019-09-11 18:06:14 -07:00

port.v

Connect queue index field in queue operation response

2019-09-01 08:29:22 -07:00

queue_manager.v

Fix pipelining bug

2019-09-13 13:48:48 -07:00

rx_checksum.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

rx_engine.v

Update rx_engine to return length

2019-09-02 08:15:07 -07:00

tdma_ber_ch.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

tdma_ber.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

tdma_scheduler.v

Parameter updates and documentation

2019-07-27 23:47:46 -07:00

tx_checksum.v

Fix latch inference

2019-08-29 18:36:15 -07:00

tx_engine.v

Update tx_engine to return status early in case of dequeue fail

2019-09-02 08:17:09 -07:00

tx_scheduler_rr.v

Improve tx_scheduler_rr timing

2019-09-14 23:32:34 -07:00

tx_scheduler_tdma_rr.v

Truncate high order address bits

2019-08-13 00:41:10 -07:00