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329 lines
12 KiB
Verilog
329 lines
12 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* PCIe TLP demultiplexer
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*/
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module pcie_tlp_demux #
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(
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// Output count
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parameter PORTS = 2,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// TLP segment data width
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parameter TLP_SEG_DATA_WIDTH = 256,
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// TLP segment strobe width
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parameter TLP_SEG_STRB_WIDTH = TLP_SEG_DATA_WIDTH/32,
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// TLP segment header width
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parameter TLP_SEG_HDR_WIDTH = 128
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)
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(
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input wire clk,
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input wire rst,
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/*
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* TLP input
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*/
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input wire [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] in_tlp_data,
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input wire [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] in_tlp_strb,
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input wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] in_tlp_hdr,
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input wire [TLP_SEG_COUNT*3-1:0] in_tlp_bar_id,
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input wire [TLP_SEG_COUNT*8-1:0] in_tlp_func_num,
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input wire [TLP_SEG_COUNT*4-1:0] in_tlp_error,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_valid,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_sop,
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input wire [TLP_SEG_COUNT-1:0] in_tlp_eop,
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output wire in_tlp_ready,
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/*
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* TLP output
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*/
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data,
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb,
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output wire [PORTS*TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr,
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output wire [PORTS*TLP_SEG_COUNT*3-1:0] out_tlp_bar_id,
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output wire [PORTS*TLP_SEG_COUNT*8-1:0] out_tlp_func_num,
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output wire [PORTS*TLP_SEG_COUNT*4-1:0] out_tlp_error,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_sop,
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output wire [PORTS*TLP_SEG_COUNT-1:0] out_tlp_eop,
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input wire [PORTS-1:0] out_tlp_ready,
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/*
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* Fields
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*/
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output wire [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] match_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] match_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] match_tlp_func_num,
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/*
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* Control
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*/
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input wire enable,
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input wire [TLP_SEG_COUNT-1:0] drop,
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input wire [TLP_SEG_COUNT*PORTS-1:0] select
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);
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parameter CL_PORTS = $clog2(PORTS);
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// check configuration
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initial begin
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if (TLP_SEG_COUNT != 1) begin
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$error("Error: TLP segment count must be 1 (instance %m)");
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$finish;
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end
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if (TLP_SEG_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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if (TLP_SEG_STRB_WIDTH*32 != TLP_SEG_DATA_WIDTH) begin
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$error("Error: PCIe interface requires dword (32-bit) granularity (instance %m)");
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$finish;
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end
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end
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reg [CL_PORTS-1:0] select_reg = {CL_PORTS{1'b0}}, select_ctl, select_next;
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reg drop_reg = 1'b0, drop_ctl, drop_next;
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reg frame_reg = 1'b0, frame_ctl, frame_next;
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reg in_tlp_ready_reg = 1'b0, in_tlp_ready_next;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_in_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_in_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_in_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] temp_in_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] temp_in_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] temp_in_tlp_error_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_valid_reg = 1'b0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_sop_reg = 1'b0;
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reg [TLP_SEG_COUNT-1:0] temp_in_tlp_eop_reg = 1'b0;
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// internal datapath
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_int;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_int;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_int;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_int;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_int;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_int;
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reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_int;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_int;
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reg out_tlp_ready_int_reg = 1'b0;
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wire out_tlp_ready_int_early;
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assign in_tlp_ready = in_tlp_ready_reg && enable;
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assign match_tlp_hdr = in_tlp_hdr;
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assign match_tlp_bar_id = in_tlp_bar_id;
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assign match_tlp_func_num = in_tlp_func_num;
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integer i;
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always @* begin
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select_next = select_reg;
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select_ctl = select_reg;
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drop_next = drop_reg;
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drop_ctl = drop_reg;
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frame_next = frame_reg;
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frame_ctl = frame_reg;
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in_tlp_ready_next = 1'b0;
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if (in_tlp_valid && in_tlp_ready) begin
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// end of frame detection
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if (in_tlp_eop) begin
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frame_next = 1'b0;
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drop_next = 1'b0;
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end
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end
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if (!frame_reg && in_tlp_valid && in_tlp_ready) begin
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// start of frame, grab select value
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select_ctl = 0;
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drop_ctl = 1'b1;
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frame_ctl = 1'b1;
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for (i = PORTS-1; i >= 0; i = i - 1) begin
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if (select[i]) begin
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select_ctl = i;
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drop_ctl = 1'b0;
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end
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end
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drop_ctl = drop_ctl || drop;
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if (!(in_tlp_ready && in_tlp_valid && in_tlp_eop)) begin
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select_next = select_ctl;
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drop_next = drop_ctl;
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frame_next = 1'b1;
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end
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end
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in_tlp_ready_next = out_tlp_ready_int_early || drop_ctl;
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out_tlp_data_int = in_tlp_data;
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out_tlp_strb_int = in_tlp_strb;
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out_tlp_hdr_int = in_tlp_hdr;
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out_tlp_bar_id_int = in_tlp_bar_id;
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out_tlp_func_num_int = in_tlp_func_num;
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out_tlp_error_int = in_tlp_error;
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out_tlp_valid_int = (in_tlp_valid && in_tlp_ready && !drop_ctl && frame_ctl) << select_ctl;
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out_tlp_sop_int = in_tlp_sop;
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out_tlp_eop_int = in_tlp_eop;
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end
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always @(posedge clk) begin
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select_reg <= select_next;
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drop_reg <= drop_next;
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frame_reg <= frame_next;
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in_tlp_ready_reg <= in_tlp_ready_next;
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if (rst) begin
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select_reg <= 2'd0;
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drop_reg <= 1'b0;
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frame_reg <= 1'b0;
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in_tlp_ready_reg <= 1'b0;
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end
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end
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// output datapath logic
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] out_tlp_error_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] out_tlp_valid_reg = 1, out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] out_tlp_eop_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH-1:0] temp_out_tlp_data_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_STRB_WIDTH-1:0] temp_out_tlp_strb_reg = 0;
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reg [TLP_SEG_COUNT*TLP_SEG_HDR_WIDTH-1:0] temp_out_tlp_hdr_reg = 0;
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reg [TLP_SEG_COUNT*3-1:0] temp_out_tlp_bar_id_reg = 0;
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reg [TLP_SEG_COUNT*8-1:0] temp_out_tlp_func_num_reg = 0;
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reg [TLP_SEG_COUNT*4-1:0] temp_out_tlp_error_reg = 0;
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reg [PORTS*TLP_SEG_COUNT-1:0] temp_out_tlp_valid_reg = 0, temp_out_tlp_valid_next;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_sop_reg = 0;
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reg [TLP_SEG_COUNT-1:0] temp_out_tlp_eop_reg = 0;
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// datapath control
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reg store_int_to_output;
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reg store_int_to_temp;
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reg store_temp_to_output;
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assign out_tlp_data = {PORTS{out_tlp_data_reg}};
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assign out_tlp_strb = {PORTS{out_tlp_strb_reg}};
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assign out_tlp_hdr = {PORTS{out_tlp_hdr_reg}};
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assign out_tlp_bar_id = {PORTS{out_tlp_bar_id_reg}};
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assign out_tlp_func_num = {PORTS{out_tlp_func_num_reg}};
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assign out_tlp_error = {PORTS{out_tlp_error_reg}};
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assign out_tlp_valid = out_tlp_valid_reg;
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assign out_tlp_sop = {PORTS{out_tlp_sop_reg}};
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assign out_tlp_eop = {PORTS{out_tlp_eop_reg}};
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign out_tlp_ready_int_early = (out_tlp_ready & out_tlp_valid) || (!temp_out_tlp_valid_reg && (!out_tlp_valid || !out_tlp_valid_int));
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always @* begin
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// transfer sink ready state to source
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out_tlp_valid_next = out_tlp_valid_reg;
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temp_out_tlp_valid_next = temp_out_tlp_valid_reg;
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store_int_to_output = 1'b0;
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store_int_to_temp = 1'b0;
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store_temp_to_output = 1'b0;
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if (out_tlp_ready_int_reg) begin
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// input is ready
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if ((out_tlp_ready & out_tlp_valid) || !out_tlp_valid) begin
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// output is ready or currently not valid, transfer data to output
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out_tlp_valid_next = out_tlp_valid_int;
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store_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_out_tlp_valid_next = out_tlp_valid_int;
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store_int_to_temp = 1'b1;
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end
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end else if (out_tlp_ready & out_tlp_valid) begin
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// input is not ready, but output is ready
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out_tlp_valid_next = temp_out_tlp_valid_reg;
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temp_out_tlp_valid_next = 1'b0;
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store_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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out_tlp_valid_reg <= {PORTS{1'b0}};
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out_tlp_ready_int_reg <= 1'b0;
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temp_out_tlp_valid_reg <= 1'b0;
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end else begin
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out_tlp_valid_reg <= out_tlp_valid_next;
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out_tlp_ready_int_reg <= out_tlp_ready_int_early;
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temp_out_tlp_valid_reg <= temp_out_tlp_valid_next;
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end
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// datapath
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if (store_int_to_output) begin
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out_tlp_data_reg <= out_tlp_data_int;
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out_tlp_strb_reg <= out_tlp_strb_int;
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out_tlp_hdr_reg <= out_tlp_hdr_int;
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out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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out_tlp_func_num_reg <= out_tlp_func_num_int;
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out_tlp_error_reg <= out_tlp_error_int;
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out_tlp_sop_reg <= out_tlp_sop_int;
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out_tlp_eop_reg <= out_tlp_eop_int;
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end else if (store_temp_to_output) begin
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out_tlp_data_reg <= temp_out_tlp_data_reg;
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out_tlp_strb_reg <= temp_out_tlp_strb_reg;
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out_tlp_hdr_reg <= temp_out_tlp_hdr_reg;
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out_tlp_bar_id_reg <= temp_out_tlp_bar_id_reg;
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out_tlp_func_num_reg <= temp_out_tlp_func_num_reg;
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out_tlp_error_reg <= temp_out_tlp_error_reg;
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out_tlp_sop_reg <= temp_out_tlp_sop_reg;
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out_tlp_eop_reg <= temp_out_tlp_eop_reg;
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end
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if (store_int_to_temp) begin
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temp_out_tlp_data_reg <= out_tlp_data_int;
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temp_out_tlp_strb_reg <= out_tlp_strb_int;
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temp_out_tlp_hdr_reg <= out_tlp_hdr_int;
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temp_out_tlp_bar_id_reg <= out_tlp_bar_id_int;
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temp_out_tlp_func_num_reg <= out_tlp_func_num_int;
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temp_out_tlp_error_reg <= out_tlp_error_int;
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temp_out_tlp_sop_reg <= out_tlp_sop_int;
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temp_out_tlp_eop_reg <= out_tlp_eop_int;
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end
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end
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endmodule
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`resetall
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