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corundum/fpga/common/rtl
History
Alex Forencich 03465b4b25 Fix parameter
2019-11-18 16:27:02 -08:00
..
cpl_op_mux.v
Add completion op mux module
2019-09-23 14:47:09 -07:00
cpl_queue_manager.v
Fix pipelining bug
2019-09-13 13:48:48 -07:00
cpl_write.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
desc_fetch.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
desc_op_mux.v
Add descriptor op mux module
2019-09-23 14:47:00 -07:00
event_mux.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
interface.v
Parametrize tag widths
2019-10-31 23:25:34 -07:00
port.v
Fix parameter
2019-11-18 16:27:02 -08:00
queue_manager.v
Fix pipelining bug
2019-09-13 13:48:48 -07:00
rx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
rx_engine.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
tdma_ber_ch.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_ber.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_scheduler.v
Update TDMA scheduler to generate status signals and avoid producing runt outputs
2019-11-05 16:55:19 -08:00
tx_checksum.v
Parametrize checksum offload
2019-11-13 23:49:50 -08:00
tx_engine.v
Use new DMA subsystem
2019-10-17 16:02:14 -07:00
tx_scheduler_ctrl_tdma.v
Add tx_scheduler_ctrl_tdma module
2019-11-05 18:24:22 -08:00
tx_scheduler_rr.v
Add scheduler control input to tx_scheduler_rr
2019-11-05 16:56:10 -08:00