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FPGA
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corundum
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corundum
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example
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VCU118
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fpga_25g
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rtl
History
Alex Forencich
2a2d8ac966
Fix reg type in VCU108 and VCU118 example designs
2020-12-20 14:22:52 -08:00
..
debounce_switch.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
fpga_core.v
Fix reg type in VCU108 and VCU118 example designs
2020-12-20 14:22:52 -08:00
fpga.v
Clean up clock connections
2020-08-06 17:15:38 -07:00
mdio_master.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
sync_signal.v
Add VCU118 25G example design
2019-06-19 23:25:06 -07:00
