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corundum/fpga/mqnic/VCU1525/fpga_25g/rtl
History
Alex Forencich 056f78716a Add pipeline registers
2022-03-17 15:39:44 -07:00
..
common
Unified 10G/25G design for VCU1525
2022-03-14 21:39:55 -07:00
debounce_switch.v
Unified 10G/25G design for VCU1525
2022-03-14 21:39:55 -07:00
fpga_core.v
Add pipeline registers
2022-03-17 15:39:44 -07:00
fpga.v
Unified 10G/25G design for VCU1525
2022-03-14 21:39:55 -07:00
sync_signal.v
Unified 10G/25G design for VCU1525
2022-03-14 21:39:55 -07:00