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523 lines
22 KiB
Verilog
523 lines
22 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI stream sink DMA client
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*/
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module dma_client_axis_sink #
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(
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2,
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// Use AXI stream tkeep signal
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parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
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// Use AXI stream tlast signal
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parameter AXIS_LAST_ENABLE = 1,
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// Propagate AXI stream tid signal
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parameter AXIS_ID_ENABLE = 0,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// Propagate AXI stream tdest signal
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parameter AXIS_DEST_ENABLE = 0,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// Propagate AXI stream tuser signal
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parameter AXIS_USER_ENABLE = 1,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Width of length field
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parameter LEN_WIDTH = 16,
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// Width of tag field
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parameter TAG_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI write descriptor input
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*/
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input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
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input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire s_axis_write_desc_valid,
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output wire s_axis_write_desc_ready,
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/*
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* AXI write descriptor status output
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*/
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output wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
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output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
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output wire m_axis_write_desc_status_valid,
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/*
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* AXI stream write data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
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/*
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* RAM interface
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*/
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output wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
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output wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
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output wire [SEG_COUNT-1:0] ram_wr_cmd_valid,
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input wire [SEG_COUNT-1:0] ram_wr_cmd_ready,
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/*
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* Configuration
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*/
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input wire enable,
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input wire abort
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);
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parameter RAM_WORD_WIDTH = SEG_BE_WIDTH;
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parameter RAM_WORD_SIZE = SEG_DATA_WIDTH/RAM_WORD_WIDTH;
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parameter AXIS_KEEP_WIDTH_INT = AXIS_KEEP_ENABLE ? AXIS_KEEP_WIDTH : 1;
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parameter AXIS_WORD_WIDTH = AXIS_KEEP_WIDTH_INT;
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parameter AXIS_WORD_SIZE = AXIS_DATA_WIDTH/AXIS_WORD_WIDTH;
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parameter PART_COUNT = SEG_COUNT*SEG_BE_WIDTH / AXIS_KEEP_WIDTH_INT;
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parameter PART_COUNT_WIDTH = PART_COUNT > 1 ? $clog2(PART_COUNT) : 1;
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parameter PART_OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter PARTS_PER_SEG = (SEG_BE_WIDTH + AXIS_KEEP_WIDTH_INT - 1) / AXIS_KEEP_WIDTH_INT;
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parameter SEGS_PER_PART = (AXIS_KEEP_WIDTH_INT + SEG_BE_WIDTH - 1) / SEG_BE_WIDTH;
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parameter OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
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parameter OFFSET_MASK = AXIS_KEEP_WIDTH_INT > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
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parameter ADDR_MASK = {RAM_ADDR_WIDTH{1'b1}} << $clog2(AXIS_KEEP_WIDTH_INT);
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parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - $clog2(AXIS_KEEP_WIDTH_INT) + 1;
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// bus width assertions
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initial begin
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if (RAM_WORD_SIZE * SEG_BE_WIDTH != SEG_DATA_WIDTH) begin
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$error("Error: RAM data width not evenly divisble (instance %m)");
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$finish;
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end
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if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
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$error("Error: AXI stream data width not evenly divisble (instance %m)");
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$finish;
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end
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if (RAM_WORD_SIZE != AXIS_WORD_SIZE) begin
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$error("Error: word size mismatch (instance %m)");
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$finish;
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end
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if (2**$clog2(RAM_WORD_WIDTH) != RAM_WORD_WIDTH) begin
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$error("Error: RAM word width must be even power of two (instance %m)");
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$finish;
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end
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if (RAM_ADDR_WIDTH != SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH)) begin
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$error("Error: RAM_ADDR_WIDTH does not match RAM configuration (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH > SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must not be wider than RAM interface width (instance %m)");
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$finish;
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end
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if (AXIS_DATA_WIDTH*2**$clog2(PART_COUNT) != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: AXI stream interface width must be a power of two fraction of RAM interface width (instance %m)");
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$finish;
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end
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end
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localparam [1:0]
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STATE_IDLE = 2'd0,
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STATE_WRITE = 2'd1,
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STATE_DROP_DATA = 2'd2;
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reg [1:0] state_reg = STATE_IDLE, state_next;
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integer i;
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reg [OFFSET_WIDTH:0] cycle_size;
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reg [RAM_ADDR_WIDTH-1:0] addr_reg = {RAM_ADDR_WIDTH{1'b0}}, addr_next;
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reg [SEG_COUNT-1:0] ram_mask_reg = 0, ram_mask_next;
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reg [AXIS_KEEP_WIDTH_INT-1:0] keep_mask_reg = {AXIS_KEEP_WIDTH_INT{1'b0}}, keep_mask_next;
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reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
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reg [LEN_WIDTH-1:0] length_reg = {LEN_WIDTH{1'b0}}, length_next;
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reg [CYCLE_COUNT_WIDTH-1:0] cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, cycle_count_next;
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reg last_cycle_reg = 1'b0, last_cycle_next;
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reg s_axis_write_desc_ready_reg = 1'b0, s_axis_write_desc_ready_next;
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reg [LEN_WIDTH-1:0] m_axis_write_desc_status_len_reg = {LEN_WIDTH{1'b0}}, m_axis_write_desc_status_len_next;
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reg [TAG_WIDTH-1:0] m_axis_write_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_write_desc_status_tag_next;
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reg [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id_reg = {AXIS_ID_WIDTH{1'b0}}, m_axis_write_desc_status_id_next;
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reg [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest_reg = {AXIS_DEST_WIDTH{1'b0}}, m_axis_write_desc_status_dest_next;
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reg [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user_reg = {AXIS_USER_WIDTH{1'b0}}, m_axis_write_desc_status_user_next;
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reg m_axis_write_desc_status_valid_reg = 1'b0, m_axis_write_desc_status_valid_next;
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reg s_axis_write_data_tready_reg = 1'b0, s_axis_write_data_tready_next;
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// internal datapath
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reg [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
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reg [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_int;
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reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_int;
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reg [SEG_COUNT-1:0] ram_wr_cmd_valid_int;
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reg [SEG_COUNT-1:0] ram_wr_cmd_ready_int_reg = 1'b0;
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wire [SEG_COUNT-1:0] ram_wr_cmd_ready_int_early;
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assign s_axis_write_desc_ready = s_axis_write_desc_ready_reg;
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assign m_axis_write_desc_status_len = m_axis_write_desc_status_len_reg;
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assign m_axis_write_desc_status_tag = m_axis_write_desc_status_tag_reg;
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assign m_axis_write_desc_status_id = m_axis_write_desc_status_id_reg;
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assign m_axis_write_desc_status_dest = m_axis_write_desc_status_dest_reg;
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assign m_axis_write_desc_status_user = m_axis_write_desc_status_user_reg;
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assign m_axis_write_desc_status_valid = m_axis_write_desc_status_valid_reg;
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assign s_axis_write_data_tready = s_axis_write_data_tready_reg;
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always @* begin
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state_next = STATE_IDLE;
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s_axis_write_desc_ready_next = 1'b0;
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m_axis_write_desc_status_len_next = m_axis_write_desc_status_len_reg;
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m_axis_write_desc_status_tag_next = m_axis_write_desc_status_tag_reg;
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m_axis_write_desc_status_id_next = m_axis_write_desc_status_id_reg;
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m_axis_write_desc_status_dest_next = m_axis_write_desc_status_dest_reg;
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m_axis_write_desc_status_user_next = m_axis_write_desc_status_user_reg;
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m_axis_write_desc_status_valid_next = 1'b0;
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s_axis_write_data_tready_next = 1'b0;
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if (PART_COUNT > 1) begin
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ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
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end else begin
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ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
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end
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ram_wr_cmd_addr_int = {PART_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
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ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
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ram_wr_cmd_valid_int = {SEG_COUNT{1'b0}};
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cycle_size = AXIS_KEEP_WIDTH_INT;
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addr_next = addr_reg;
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ram_mask_next = ram_mask_reg;
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keep_mask_next = keep_mask_reg;
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last_cycle_offset_next = last_cycle_offset_reg;
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length_next = length_reg;
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cycle_count_next = cycle_count_reg;
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last_cycle_next = last_cycle_reg;
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case (state_reg)
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STATE_IDLE: begin
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// idle state - load new descriptor to start operation
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s_axis_write_desc_ready_next = enable;
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addr_next = s_axis_write_desc_ram_addr & ADDR_MASK;
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last_cycle_offset_next = s_axis_write_desc_len & OFFSET_MASK;
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if (PART_COUNT > 1) begin
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ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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ram_mask_next = {SEG_COUNT{1'b1}};
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end
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m_axis_write_desc_status_tag_next = s_axis_write_desc_tag;
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length_next = 0;
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cycle_count_next = (s_axis_write_desc_len - 1) >> $clog2(AXIS_KEEP_WIDTH_INT);
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last_cycle_next = cycle_count_next == 0;
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if (cycle_count_next == 0 && last_cycle_offset_next != 0) begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_next);
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end else begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
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end
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if (s_axis_write_desc_ready && s_axis_write_desc_valid) begin
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s_axis_write_desc_ready_next = 1'b0;
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s_axis_write_data_tready_next = !(~ram_wr_cmd_ready_int_early & ram_mask_next);
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state_next = STATE_WRITE;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_WRITE: begin
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// write state - generate write operations
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s_axis_write_data_tready_next = !(~ram_wr_cmd_ready_int_early & ram_mask_reg);
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if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
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m_axis_write_desc_status_id_next = s_axis_write_data_tid;
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m_axis_write_desc_status_dest_next = s_axis_write_data_tdest;
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m_axis_write_desc_status_user_next = s_axis_write_data_tuser;
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// update counters
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addr_next = addr_reg + AXIS_KEEP_WIDTH_INT;
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length_next = length_reg + AXIS_KEEP_WIDTH_INT;
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cycle_count_next = cycle_count_reg - 1;
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last_cycle_next = cycle_count_next == 0;
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if (cycle_count_next == 0 && last_cycle_offset_reg != 0) begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg);
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end else begin
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keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
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end
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if (PART_COUNT > 1) begin
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ram_mask_next = {SEGS_PER_PART{1'b1}} << ((((addr_next >> PART_OFFSET_WIDTH) & ({PART_COUNT_WIDTH{1'b1}})) / PARTS_PER_SEG) * SEGS_PER_PART);
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end else begin
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ram_mask_next = {SEG_COUNT{1'b1}};
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end
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if (PART_COUNT > 1) begin
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ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
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end else begin
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ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
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end
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ram_wr_cmd_addr_int = {SEG_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
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ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
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for (i = 0; i < SEG_COUNT; i = i + 1) begin
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ram_wr_cmd_valid_int[i] = ram_wr_cmd_be_int[i*SEG_BE_WIDTH +: SEG_BE_WIDTH] != 0;
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end
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if (AXIS_LAST_ENABLE && s_axis_write_data_tlast) begin
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if (AXIS_KEEP_ENABLE) begin
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cycle_size = AXIS_KEEP_WIDTH_INT;
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for (i = AXIS_KEEP_WIDTH_INT-1; i >= 0; i = i - 1) begin
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if (~(s_axis_write_data_tkeep & keep_mask_reg) & (1 << i)) begin
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cycle_size = i;
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end
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end
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end else begin
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cycle_size = AXIS_KEEP_WIDTH_INT;
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end
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// no more data to transfer, finish operation
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if (last_cycle_reg && last_cycle_offset_reg > 0) begin
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if (AXIS_KEEP_ENABLE && !(s_axis_write_data_tkeep & keep_mask_reg & ~({AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg)))) begin
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length_next = length_reg + cycle_size;
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end else begin
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length_next = length_reg + last_cycle_offset_reg;
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end
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end else begin
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if (AXIS_KEEP_ENABLE) begin
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length_next = length_reg + cycle_size;
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end
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end
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m_axis_write_desc_status_len_next = length_next;
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m_axis_write_desc_status_valid_next = 1'b1;
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s_axis_write_data_tready_next = 1'b0;
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s_axis_write_desc_ready_next = enable;
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state_next = STATE_IDLE;
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end else if (last_cycle_reg) begin
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if (last_cycle_offset_reg > 0) begin
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length_next = length_reg + last_cycle_offset_reg;
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end
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m_axis_write_desc_status_len_next = length_next;
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m_axis_write_desc_status_valid_next = 1'b1;
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if (AXIS_LAST_ENABLE) begin
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s_axis_write_data_tready_next = 1'b1;
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state_next = STATE_DROP_DATA;
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end else begin
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s_axis_write_data_tready_next = 1'b0;
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s_axis_write_desc_ready_next = enable;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_WRITE;
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end
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end else begin
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state_next = STATE_WRITE;
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end
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end
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STATE_DROP_DATA: begin
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// drop excess AXI stream data
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s_axis_write_data_tready_next = 1'b1;
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if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
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if (s_axis_write_data_tlast) begin
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s_axis_write_data_tready_next = 1'b0;
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s_axis_write_desc_ready_next = enable;
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_DROP_DATA;
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|
end
|
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end else begin
|
|
state_next = STATE_DROP_DATA;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
state_reg <= state_next;
|
|
|
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s_axis_write_desc_ready_reg <= s_axis_write_desc_ready_next;
|
|
|
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m_axis_write_desc_status_len_reg <= m_axis_write_desc_status_len_next;
|
|
m_axis_write_desc_status_tag_reg <= m_axis_write_desc_status_tag_next;
|
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m_axis_write_desc_status_id_reg <= m_axis_write_desc_status_id_next;
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|
m_axis_write_desc_status_dest_reg <= m_axis_write_desc_status_dest_next;
|
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m_axis_write_desc_status_user_reg <= m_axis_write_desc_status_user_next;
|
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m_axis_write_desc_status_valid_reg <= m_axis_write_desc_status_valid_next;
|
|
|
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s_axis_write_data_tready_reg <= s_axis_write_data_tready_next;
|
|
|
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addr_reg <= addr_next;
|
|
ram_mask_reg <= ram_mask_next;
|
|
keep_mask_reg <= keep_mask_next;
|
|
last_cycle_offset_reg <= last_cycle_offset_next;
|
|
length_reg <= length_next;
|
|
cycle_count_reg <= cycle_count_next;
|
|
last_cycle_reg <= last_cycle_next;
|
|
|
|
if (rst) begin
|
|
state_reg <= STATE_IDLE;
|
|
s_axis_write_desc_ready_reg <= 1'b0;
|
|
m_axis_write_desc_status_valid_reg <= 1'b0;
|
|
s_axis_write_data_tready_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// output datapath logic (write data)
|
|
generate
|
|
|
|
genvar n;
|
|
|
|
for (n = 0; n < SEG_COUNT; n = n + 1) begin
|
|
|
|
reg [SEG_BE_WIDTH-1:0] ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
|
|
reg [SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
|
|
reg [SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
|
|
reg ram_wr_cmd_valid_reg = 1'b0, ram_wr_cmd_valid_next;
|
|
|
|
reg [SEG_BE_WIDTH-1:0] temp_ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
|
|
reg [SEG_ADDR_WIDTH-1:0] temp_ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
|
|
reg [SEG_DATA_WIDTH-1:0] temp_ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
|
|
reg temp_ram_wr_cmd_valid_reg = 1'b0, temp_ram_wr_cmd_valid_next;
|
|
|
|
// datapath control
|
|
reg store_axi_w_int_to_output;
|
|
reg store_axi_w_int_to_temp;
|
|
reg store_axi_w_temp_to_output;
|
|
|
|
assign ram_wr_cmd_be[n*SEG_BE_WIDTH +: SEG_BE_WIDTH] = ram_wr_cmd_be_reg;
|
|
assign ram_wr_cmd_addr[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = ram_wr_cmd_addr_reg;
|
|
assign ram_wr_cmd_data[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = ram_wr_cmd_data_reg;
|
|
assign ram_wr_cmd_valid[n +: 1] = ram_wr_cmd_valid_reg;
|
|
|
|
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
|
assign ram_wr_cmd_ready_int_early[n +: 1] = ram_wr_cmd_ready[n +: 1] || (!temp_ram_wr_cmd_valid_reg && (!ram_wr_cmd_valid_reg || !ram_wr_cmd_valid_int[n +: 1]));
|
|
|
|
always @* begin
|
|
// transfer sink ready state to source
|
|
ram_wr_cmd_valid_next = ram_wr_cmd_valid_reg;
|
|
temp_ram_wr_cmd_valid_next = temp_ram_wr_cmd_valid_reg;
|
|
|
|
store_axi_w_int_to_output = 1'b0;
|
|
store_axi_w_int_to_temp = 1'b0;
|
|
store_axi_w_temp_to_output = 1'b0;
|
|
|
|
if (ram_wr_cmd_ready_int_reg[n +: 1]) begin
|
|
// input is ready
|
|
if (ram_wr_cmd_ready[n +: 1] || !ram_wr_cmd_valid_reg) begin
|
|
// output is ready or currently not valid, transfer data to output
|
|
ram_wr_cmd_valid_next = ram_wr_cmd_valid_int[n +: 1];
|
|
store_axi_w_int_to_output = 1'b1;
|
|
end else begin
|
|
// output is not ready, store input in temp
|
|
temp_ram_wr_cmd_valid_next = ram_wr_cmd_valid_int[n +: 1];
|
|
store_axi_w_int_to_temp = 1'b1;
|
|
end
|
|
end else if (ram_wr_cmd_ready[n +: 1]) begin
|
|
// input is not ready, but output is ready
|
|
ram_wr_cmd_valid_next = temp_ram_wr_cmd_valid_reg;
|
|
temp_ram_wr_cmd_valid_next = 1'b0;
|
|
store_axi_w_temp_to_output = 1'b1;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
ram_wr_cmd_valid_reg <= 1'b0;
|
|
ram_wr_cmd_ready_int_reg[n +: 1] <= 1'b0;
|
|
temp_ram_wr_cmd_valid_reg <= 1'b0;
|
|
end else begin
|
|
ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_next;
|
|
ram_wr_cmd_ready_int_reg[n +: 1] <= ram_wr_cmd_ready_int_early[n +: 1];
|
|
temp_ram_wr_cmd_valid_reg <= temp_ram_wr_cmd_valid_next;
|
|
end
|
|
|
|
// datapath
|
|
if (store_axi_w_int_to_output) begin
|
|
ram_wr_cmd_be_reg <= ram_wr_cmd_be_int[n*SEG_BE_WIDTH +: SEG_BE_WIDTH];
|
|
ram_wr_cmd_addr_reg <= ram_wr_cmd_addr_int[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
|
|
ram_wr_cmd_data_reg <= ram_wr_cmd_data_int[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
|
|
end else if (store_axi_w_temp_to_output) begin
|
|
ram_wr_cmd_be_reg <= temp_ram_wr_cmd_be_reg;
|
|
ram_wr_cmd_addr_reg <= temp_ram_wr_cmd_addr_reg;
|
|
ram_wr_cmd_data_reg <= temp_ram_wr_cmd_data_reg;
|
|
end
|
|
|
|
if (store_axi_w_int_to_temp) begin
|
|
temp_ram_wr_cmd_be_reg <= ram_wr_cmd_be_int[n*SEG_BE_WIDTH +: SEG_BE_WIDTH];
|
|
temp_ram_wr_cmd_addr_reg <= ram_wr_cmd_addr_int[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
|
|
temp_ram_wr_cmd_data_reg <= ram_wr_cmd_data_int[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
|
|
end
|
|
end
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
endmodule
|