mirror of
https://github.com/corundum/corundum.git
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478 lines
16 KiB
Python
Executable File
478 lines
16 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an AXI Stream switch with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if type(ports) is int:
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m = n = ports
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elif len(ports) == 1:
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m = n = ports[0]
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else:
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m, n = ports
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if name is None:
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name = "axis_switch_{0}x{1}".format(m, n)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0}x{1} port AXI Stream switch {2}...".format(m, n, name))
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cm = int(math.ceil(math.log(m, 2)))
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cn = int(math.ceil(math.log(n, 2)))
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t = Template(u"""/*
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Copyright (c) 2016 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream {{m}}x{{n}} switch
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*/
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module {{name}} #
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(
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parameter DATA_WIDTH = 8,
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parameter DEST_WIDTH = {{cn}},
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{%- for p in range(n) %}
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parameter OUT_{{p}}_BASE = {{p}},
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parameter OUT_{{p}}_TOP = {{p}},
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parameter OUT_{{p}}_CONNECT = {{m}}'b{% for p in range(m) %}1{% endfor %},
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{%- endfor %}
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// arbitration type: "PRIORITY" or "ROUND_ROBIN"
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parameter ARB_TYPE = "ROUND_ROBIN",
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// LSB priority: "LOW", "HIGH"
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parameter LSB_PRIORITY = "HIGH"
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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{%- for p in range(m) %}
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input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
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input wire input_{{p}}_axis_tvalid,
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output wire input_{{p}}_axis_tready,
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input wire input_{{p}}_axis_tlast,
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input wire [DEST_WIDTH-1:0] input_{{p}}_axis_tdest,
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input wire input_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* AXI Stream outputs
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*/
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{%- for p in range(n) %}
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output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
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output wire output_{{p}}_axis_tvalid,
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input wire output_{{p}}_axis_tready,
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output wire output_{{p}}_axis_tlast,
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output wire [DEST_WIDTH-1:0] output_{{p}}_axis_tdest,
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output wire output_{{p}}_axis_tuser{% if not loop.last %},{% endif %}
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{% endfor -%}
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);
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// check configuration
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initial begin
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if (2**DEST_WIDTH < {{n}}) begin
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$error("Error: DEST_WIDTH too small for port count");
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$finish;
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end
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if ({%- for p in range(n) %}(OUT_{{p}}_BASE & 2**DEST_WIDTH-1) != OUT_{{p}}_BASE || (OUT_{{p}}_TOP & 2**DEST_WIDTH-1) != OUT_{{p}}_TOP{% if not loop.last %} ||
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{% endif %}{% endfor -%}) begin
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$error("Error: value out of range");
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$finish;
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end
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if ({%- for p in range(n) %}OUT_{{p}}_BASE > OUT_{{p}}_TOP{% if not loop.last %} ||
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{% endif %}{% endfor -%}) begin
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$error("Error: invalid range");
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$finish;
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end
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if ({%- for p in range(n-1) %}{% set outer_loop = loop %}{%- for q in range(p+1,n) %}(OUT_{{p}}_BASE <= OUT_{{q}}_TOP && OUT_{{q}}_BASE <= OUT_{{p}}_TOP){% if not (loop.last and outer_loop.last) %} ||
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{% endif %}{% endfor -%}{% endfor -%}) begin
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$error("Error: ranges overlap");
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$finish;
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end
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end
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{%- for p in range(m) %}
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reg [{{n-1}}:0] input_{{p}}_request_reg = {{n}}'d0, input_{{p}}_request_next;
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reg input_{{p}}_request_valid_reg = 1'b0, input_{{p}}_request_valid_next;
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reg input_{{p}}_request_error_reg = 1'b0, input_{{p}}_request_error_next;
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{%- endfor %}
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{% for p in range(n) %}
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reg [{{cm-1}}:0] select_{{p}}_reg = {{cm}}'d0, select_{{p}}_next;
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{%- endfor %}
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{% for p in range(n) %}
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reg enable_{{p}}_reg = 1'b0, enable_{{p}}_next;
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{%- endfor %}
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{% for p in range(m) %}
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reg input_{{p}}_axis_tready_reg = 1'b0, input_{{p}}_axis_tready_next;
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{%- endfor %}
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// internal datapath
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{%- for p in range(n) %}
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reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_int;
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reg output_{{p}}_axis_tvalid_int;
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reg output_{{p}}_axis_tready_int_reg = 1'b0;
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reg output_{{p}}_axis_tlast_int;
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reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_int;
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reg output_{{p}}_axis_tuser_int;
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wire output_{{p}}_axis_tready_int_early;
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{% endfor %}
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{%- for p in range(m) %}
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assign input_{{p}}_axis_tready = input_{{p}}_axis_tready_reg;
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{%- endfor %}
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// mux for start of packet detection
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{%- for p in range(n) %}
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reg selected_input_{{p}}_axis_tvalid;
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always @* begin
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case (grant_encoded_{{p}})
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{%- for q in range(m) %}
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{{cm}}'d{{q}}: selected_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
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{%- endfor %}
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default: selected_input_{{p}}_axis_tvalid = 1'b0;
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endcase
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end
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{% endfor %}
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// mux for incoming packet
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{% for p in range(n) %}
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reg [DATA_WIDTH-1:0] current_input_{{p}}_axis_tdata;
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reg current_input_{{p}}_axis_tvalid;
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reg current_input_{{p}}_axis_tready;
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reg current_input_{{p}}_axis_tlast;
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reg [DEST_WIDTH-1:0] current_input_{{p}}_axis_tdest;
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reg current_input_{{p}}_axis_tuser;
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always @* begin
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case (select_{{p}}_reg)
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{%- for q in range(m) %}
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{{cm}}'d{{q}}: begin
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current_input_{{p}}_axis_tdata = input_{{q}}_axis_tdata;
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current_input_{{p}}_axis_tvalid = input_{{q}}_axis_tvalid;
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current_input_{{p}}_axis_tready = input_{{q}}_axis_tready;
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current_input_{{p}}_axis_tlast = input_{{q}}_axis_tlast;
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current_input_{{p}}_axis_tdest = input_{{q}}_axis_tdest;
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current_input_{{p}}_axis_tuser = input_{{q}}_axis_tuser;
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end
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{%- endfor %}
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default: begin
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current_input_{{p}}_axis_tdata = {DATA_WIDTH{1'b0}};
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current_input_{{p}}_axis_tvalid = 1'b0;
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current_input_{{p}}_axis_tready = 1'b0;
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current_input_{{p}}_axis_tlast = 1'b0;
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current_input_{{p}}_axis_tdest = {DEST_WIDTH{1'b0}};
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current_input_{{p}}_axis_tuser = 1'b0;
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end
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endcase
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end
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{% endfor %}
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// arbiter instances
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{% for p in range(n) %}
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wire [{{m-1}}:0] request_{{p}};
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wire [{{m-1}}:0] acknowledge_{{p}};
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wire [{{m-1}}:0] grant_{{p}};
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wire grant_valid_{{p}};
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wire [{{cm-1}}:0] grant_encoded_{{p}};
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{% endfor %}
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{%- for p in range(n) %}
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arbiter #(
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.PORTS({{m}}),
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.TYPE(ARB_TYPE),
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.BLOCK("ACKNOWLEDGE"),
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.LSB_PRIORITY(LSB_PRIORITY)
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)
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arb_{{p}}_inst (
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.clk(clk),
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.rst(rst),
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.request(request_{{p}}),
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.acknowledge(acknowledge_{{p}}),
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.grant(grant_{{p}}),
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.grant_valid(grant_valid_{{p}}),
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.grant_encoded(grant_encoded_{{p}})
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);
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{% endfor %}
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// request generation
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{%- for p in range(n) %}
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{%- for q in range(m) %}
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assign request_{{p}}[{{q}}] = input_{{q}}_request_reg[{{p}}] & ~acknowledge_{{p}}[{{q}}];
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{%- endfor %}
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{% endfor %}
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// acknowledge generation
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{%- for p in range(n) %}
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{%- for q in range(m) %}
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assign acknowledge_{{p}}[{{q}}] = grant_{{p}}[{{q}}] & input_{{q}}_axis_tvalid & input_{{q}}_axis_tready & input_{{q}}_axis_tlast;
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{%- endfor %}
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{% endfor %}
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always @* begin
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{%- for p in range(n) %}
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select_{{p}}_next = select_{{p}}_reg;
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{%- endfor %}
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{% for p in range(n) %}
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enable_{{p}}_next = enable_{{p}}_reg;
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{%- endfor %}
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{% for p in range(m) %}
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input_{{p}}_request_next = input_{{p}}_request_reg;
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input_{{p}}_request_valid_next = input_{{p}}_request_valid_reg;
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input_{{p}}_request_error_next = input_{{p}}_request_error_reg;
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{% endfor %}
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{%- for p in range(m) %}
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input_{{p}}_axis_tready_next = 1'b0;
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{%- endfor %}
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{% for p in range(n) %}
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output_{{p}}_axis_tdata_int = {DATA_WIDTH{1'b0}};
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output_{{p}}_axis_tvalid_int = 1'b0;
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output_{{p}}_axis_tlast_int = 1'b0;
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output_{{p}}_axis_tdest_int = {DEST_WIDTH{1'b0}};
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output_{{p}}_axis_tuser_int = 1'b0;
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{% endfor %}
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// input decoding
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{% for p in range(m) %}
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if (input_{{p}}_request_valid_reg | input_{{p}}_request_error_reg) begin
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if (input_{{p}}_axis_tvalid & input_{{p}}_axis_tready & input_{{p}}_axis_tlast) begin
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input_{{p}}_request_next = {DEST_WIDTH{1'b0}};
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input_{{p}}_request_valid_next = 1'b0;
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input_{{p}}_request_error_next = 1'b0;
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end
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end else if (input_{{p}}_axis_tvalid) begin
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{%- for q in range(n) %}
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input_{{p}}_request_next[{{q}}] = (input_{{p}}_axis_tdest >= OUT_{{q}}_BASE) & (input_{{p}}_axis_tdest <= OUT_{{q}}_TOP) & OUT_{{q}}_CONNECT[{{p}}];
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{%- endfor %}
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if (input_{{p}}_request_next) begin
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input_{{p}}_request_valid_next = 1'b1;
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end else begin
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input_{{p}}_request_error_next = 1'b1;
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end
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end
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{% endfor %}
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// output control
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{% for p in range(n) %}
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if (enable_{{p}}_reg) begin
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if (current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready) begin
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enable_{{p}}_next = ~current_input_{{p}}_axis_tlast;
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end
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end else if (grant_valid_{{p}} & selected_input_{{p}}_axis_tvalid) begin
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enable_{{p}}_next = 1'b1;
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select_{{p}}_next = grant_encoded_{{p}};
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end
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{% endfor %}
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// generate ready signal on selected port
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{% for p in range(n) %}
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if (enable_{{p}}_next) begin
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case (select_{{p}}_next)
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{%- for q in range(m) %}
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{{cm}}'d{{q}}: input_{{q}}_axis_tready_next = output_{{p}}_axis_tready_int_early;
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{%- endfor %}
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endcase
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end
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{% endfor %}
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{%- for p in range(m) %}
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if (input_{{p}}_request_error_next)
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input_{{p}}_axis_tready_next = 1'b1;
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{%- endfor %}
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// pass through selected packet data
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{% for p in range(n) %}
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output_{{p}}_axis_tdata_int = current_input_{{p}}_axis_tdata;
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output_{{p}}_axis_tvalid_int = current_input_{{p}}_axis_tvalid & current_input_{{p}}_axis_tready & enable_{{p}}_reg;
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output_{{p}}_axis_tlast_int = current_input_{{p}}_axis_tlast;
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output_{{p}}_axis_tdest_int = current_input_{{p}}_axis_tdest;
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output_{{p}}_axis_tuser_int = current_input_{{p}}_axis_tuser;
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{% endfor -%}
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end
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always @(posedge clk) begin
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if (rst) begin
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{%- for p in range(m) %}
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input_{{p}}_request_reg <= {{n}}'d0;
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input_{{p}}_request_valid_reg <= 1'b0;
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input_{{p}}_request_error_reg <= 1'b0;
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{%- endfor %}
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{%- for p in range(n) %}
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select_{{p}}_reg <= 2'd0;
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{%- endfor %}
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{%- for p in range(n) %}
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enable_{{p}}_reg <= 1'b0;
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{%- endfor %}
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{%- for p in range(m) %}
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input_{{p}}_axis_tready_reg <= 1'b0;
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{%- endfor %}
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end else begin
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{%- for p in range(m) %}
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input_{{p}}_request_reg <= input_{{p}}_request_next;
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input_{{p}}_request_valid_reg <= input_{{p}}_request_valid_next;
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input_{{p}}_request_error_reg <= input_{{p}}_request_error_next;
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{%- endfor %}
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{%- for p in range(n) %}
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select_{{p}}_reg <= select_{{p}}_next;
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{%- endfor %}
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{%- for p in range(n) %}
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enable_{{p}}_reg <= enable_{{p}}_next;
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{%- endfor %}
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{%- for p in range(m) %}
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input_{{p}}_axis_tready_reg <= input_{{p}}_axis_tready_next;
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{%- endfor %}
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end
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end
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{% for p in range(n) %}
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// output {{p}} datapath logic
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reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg output_{{p}}_axis_tvalid_reg = 1'b0, output_{{p}}_axis_tvalid_next;
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reg output_{{p}}_axis_tlast_reg = 1'b0;
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reg [DEST_WIDTH-1:0] output_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg output_{{p}}_axis_tuser_reg = 1'b0;
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reg [DATA_WIDTH-1:0] temp_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg temp_{{p}}_axis_tvalid_reg = 1'b0, temp_{{p}}_axis_tvalid_next;
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reg temp_{{p}}_axis_tlast_reg = 1'b0;
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reg [DEST_WIDTH-1:0] temp_{{p}}_axis_tdest_reg = {DEST_WIDTH{1'b0}};
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reg temp_{{p}}_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_{{p}}_axis_int_to_output;
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reg store_{{p}}_axis_int_to_temp;
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reg store_{{p}}_axis_temp_to_output;
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assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
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assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
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assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
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assign output_{{p}}_axis_tdest = output_{{p}}_axis_tdest_reg;
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assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign output_{{p}}_axis_tready_int_early = output_{{p}}_axis_tready | (~temp_{{p}}_axis_tvalid_reg & (~output_{{p}}_axis_tvalid_reg | ~output_{{p}}_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_reg;
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temp_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
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store_{{p}}_axis_int_to_output = 1'b0;
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store_{{p}}_axis_int_to_temp = 1'b0;
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store_{{p}}_axis_temp_to_output = 1'b0;
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if (output_{{p}}_axis_tready_int_reg) begin
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// input is ready
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if (output_{{p}}_axis_tready | ~output_{{p}}_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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output_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
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store_{{p}}_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_{{p}}_axis_tvalid_next = output_{{p}}_axis_tvalid_int;
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store_{{p}}_axis_int_to_temp = 1'b1;
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end
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end else if (output_{{p}}_axis_tready) begin
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// input is not ready, but output is ready
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output_{{p}}_axis_tvalid_next = temp_{{p}}_axis_tvalid_reg;
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temp_{{p}}_axis_tvalid_next = 1'b0;
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store_{{p}}_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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output_{{p}}_axis_tvalid_reg <= 1'b0;
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output_{{p}}_axis_tready_int_reg <= 1'b0;
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temp_{{p}}_axis_tvalid_reg <= 1'b0;
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end else begin
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output_{{p}}_axis_tvalid_reg <= output_{{p}}_axis_tvalid_next;
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output_{{p}}_axis_tready_int_reg <= output_{{p}}_axis_tready_int_early;
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temp_{{p}}_axis_tvalid_reg <= temp_{{p}}_axis_tvalid_next;
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end
|
|
|
|
// datapath
|
|
if (store_{{p}}_axis_int_to_output) begin
|
|
output_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
|
output_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
|
output_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
|
output_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
|
end else if (store_{{p}}_axis_temp_to_output) begin
|
|
output_{{p}}_axis_tdata_reg <= temp_{{p}}_axis_tdata_reg;
|
|
output_{{p}}_axis_tlast_reg <= temp_{{p}}_axis_tlast_reg;
|
|
output_{{p}}_axis_tdest_reg <= temp_{{p}}_axis_tdest_reg;
|
|
output_{{p}}_axis_tuser_reg <= temp_{{p}}_axis_tuser_reg;
|
|
end
|
|
|
|
if (store_{{p}}_axis_int_to_temp) begin
|
|
temp_{{p}}_axis_tdata_reg <= output_{{p}}_axis_tdata_int;
|
|
temp_{{p}}_axis_tlast_reg <= output_{{p}}_axis_tlast_int;
|
|
temp_{{p}}_axis_tdest_reg <= output_{{p}}_axis_tdest_int;
|
|
temp_{{p}}_axis_tuser_reg <= output_{{p}}_axis_tuser_int;
|
|
end
|
|
end
|
|
{% endfor %}
|
|
endmodule
|
|
|
|
""")
|
|
|
|
output_file.write(t.render(
|
|
m=m,
|
|
n=n,
|
|
cm=cm,
|
|
cn=cn,
|
|
name=name
|
|
))
|
|
|
|
print("Done")
|
|
|
|
if __name__ == "__main__":
|
|
main()
|
|
|