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394 lines
16 KiB
Verilog
394 lines
16 KiB
Verilog
/*
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Copyright (c) 2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Intel Stratix 10 H-Tile/L-Tile PCIe interface adapter (receive)
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*/
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module pcie_s10_if_rx #
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(
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// H-Tile/L-Tile AVST segment count
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parameter SEG_COUNT = 1,
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// H-Tile/L-Tile AVST segment data width
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parameter SEG_DATA_WIDTH = 256,
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// H-Tile/L-Tile AVST segment empty signal width
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parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
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// TLP data width
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parameter TLP_DATA_WIDTH = SEG_COUNT*SEG_DATA_WIDTH,
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// TLP strobe width
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parameter TLP_STRB_WIDTH = TLP_DATA_WIDTH/32,
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// TLP header width
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parameter TLP_HDR_WIDTH = 128,
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// TLP segment count
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parameter TLP_SEG_COUNT = 1,
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// IO bar index
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// rx_st_bar_range = 6 is mapped to IO_BAR_INDEX on rx_req_tlp_bar_id
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parameter IO_BAR_INDEX = 5
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)
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(
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input wire clk,
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input wire rst,
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/*
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* H-Tile/L-Tile RX AVST interface
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*/
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input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
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input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
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input wire [SEG_COUNT-1:0] rx_st_sop,
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input wire [SEG_COUNT-1:0] rx_st_eop,
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input wire [SEG_COUNT-1:0] rx_st_valid,
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output wire rx_st_ready,
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input wire [SEG_COUNT-1:0] rx_st_vf_active,
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input wire [SEG_COUNT*2-1:0] rx_st_func_num,
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input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
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input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
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/*
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* TLP output (request to BAR)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_req_tlp_data,
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output wire [TLP_STRB_WIDTH-1:0] rx_req_tlp_strb,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_req_tlp_hdr,
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output wire [TLP_SEG_COUNT*3-1:0] rx_req_tlp_bar_id,
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output wire [TLP_SEG_COUNT*8-1:0] rx_req_tlp_func_num,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_req_tlp_eop,
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input wire rx_req_tlp_ready,
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/*
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* TLP output (completion to DMA)
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*/
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output wire [TLP_DATA_WIDTH-1:0] rx_cpl_tlp_data,
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output wire [TLP_STRB_WIDTH-1:0] rx_cpl_tlp_strb,
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output wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_cpl_tlp_hdr,
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output wire [TLP_SEG_COUNT*4-1:0] rx_cpl_tlp_error,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_valid,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_sop,
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output wire [TLP_SEG_COUNT-1:0] rx_cpl_tlp_eop,
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input wire rx_cpl_tlp_ready
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);
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parameter SEG_STRB_WIDTH = SEG_DATA_WIDTH/32;
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parameter INT_TLP_SEG_COUNT = SEG_COUNT;
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parameter INT_TLP_SEG_DATA_WIDTH = TLP_DATA_WIDTH / INT_TLP_SEG_COUNT;
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parameter INT_TLP_SEG_STRB_WIDTH = TLP_STRB_WIDTH / INT_TLP_SEG_COUNT;
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// bus width assertions
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initial begin
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if (SEG_DATA_WIDTH != 256) begin
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$error("Error: segment data width must be 256 (instance %m)");
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$finish;
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end
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if (TLP_DATA_WIDTH != SEG_COUNT*SEG_DATA_WIDTH) begin
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$error("Error: Interface widths must match (instance %m)");
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$finish;
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end
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if (TLP_HDR_WIDTH != 128) begin
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$error("Error: TLP segment header width must be 128 (instance %m)");
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$finish;
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end
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end
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reg [TLP_DATA_WIDTH-1:0] rx_tlp_data_reg = 0, rx_tlp_data_next;
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reg [TLP_STRB_WIDTH-1:0] rx_tlp_strb_reg = 0, rx_tlp_strb_next;
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reg [INT_TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] rx_tlp_hdr_reg = 0, rx_tlp_hdr_next;
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reg [INT_TLP_SEG_COUNT*3-1:0] rx_tlp_bar_id_reg = 0, rx_tlp_bar_id_next;
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reg [INT_TLP_SEG_COUNT*8-1:0] rx_tlp_func_num_reg = 0, rx_tlp_func_num_next;
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reg [INT_TLP_SEG_COUNT-1:0] rx_tlp_valid_reg = 0, rx_tlp_valid_next;
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reg [INT_TLP_SEG_COUNT-1:0] rx_tlp_sop_reg = 0, rx_tlp_sop_next;
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reg [INT_TLP_SEG_COUNT-1:0] rx_tlp_eop_reg = 0, rx_tlp_eop_next;
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reg tlp_hdr_4dw_reg = 0, tlp_hdr_4dw_next;
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wire fifo_tlp_ready;
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wire [1:0] fifo_watermark;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb_sop;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb_eop;
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reg [TLP_DATA_WIDTH-1:0] rx_st_data_int_reg = 0, rx_st_data_int_next;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb_int_reg = 0, rx_st_strb_int_next;
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reg [SEG_COUNT-1:0] rx_st_sop_int_reg = 0, rx_st_sop_int_next;
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reg [SEG_COUNT-1:0] rx_st_eop_int_reg = 0, rx_st_eop_int_next;
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reg [SEG_COUNT-1:0] rx_st_valid_int_reg = 0, rx_st_valid_int_next;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb_sop_int_reg = 0, rx_st_strb_sop_int_next;
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reg [TLP_STRB_WIDTH-1:0] rx_st_strb_eop_int_reg = 0, rx_st_strb_eop_int_next;
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reg [SEG_COUNT-1:0] rx_st_vf_active_int_reg = 0, rx_st_vf_active_int_next;
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reg [SEG_COUNT*2-1:0] rx_st_func_num_int_reg = 0, rx_st_func_num_int_next;
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reg [SEG_COUNT*11-1:0] rx_st_vf_num_int_reg = 0, rx_st_vf_num_int_next;
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reg [SEG_COUNT*3-1:0] rx_st_bar_range_int_reg = 0, rx_st_bar_range_int_next;
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wire [TLP_DATA_WIDTH*2-1:0] rx_st_data_full = {rx_st_data, rx_st_data_int_reg};
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wire [TLP_STRB_WIDTH*2-1:0] rx_st_strb_full = {rx_st_strb, rx_st_strb_int_reg};
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wire [SEG_COUNT*2-1:0] rx_st_sop_full = {rx_st_sop, rx_st_sop_int_reg};
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wire [SEG_COUNT*2-1:0] rx_st_eop_full = {rx_st_eop, rx_st_eop_int_reg};
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wire [SEG_COUNT*2-1:0] rx_st_valid_full = {rx_st_valid, rx_st_valid_int_reg};
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wire [TLP_STRB_WIDTH*2-1:0] rx_st_strb_sop_full = {rx_st_strb_sop, rx_st_strb_sop_int_reg};
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wire [TLP_STRB_WIDTH*2-1:0] rx_st_strb_eop_full = {rx_st_strb_eop, rx_st_strb_eop_int_reg};
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wire [SEG_COUNT*2-1:0] rx_st_vf_active_full = {rx_st_vf_active, rx_st_vf_active_int_reg};
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wire [SEG_COUNT*2*2-1:0] rx_st_func_num_full = {rx_st_func_num, rx_st_func_num_int_reg};
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wire [SEG_COUNT*2*11-1:0] rx_st_vf_num_full = {rx_st_vf_num, rx_st_vf_num_int_reg};
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wire [SEG_COUNT*2*3-1:0] rx_st_bar_range_full = {rx_st_bar_range, rx_st_bar_range_int_reg};
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reg [INT_TLP_SEG_COUNT*128-1:0] tlp_hdr;
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reg [INT_TLP_SEG_COUNT*3-1:0] tlp_bar_id;
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reg [INT_TLP_SEG_COUNT*8-1:0] tlp_func_num;
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assign rx_st_ready = !fifo_watermark;
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// demux w/FIFOs
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wire [INT_TLP_SEG_COUNT*128-1:0] demux_match_tlp_hdr;
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wire [INT_TLP_SEG_COUNT-1:0] demux_drop = 0;
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wire [2*INT_TLP_SEG_COUNT-1:0] demux_select;
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generate
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genvar m, n;
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for (n = 0; n < INT_TLP_SEG_COUNT; n = n + 1) begin
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// send completions to port 1 (fmt/type 8'b0x0_0101x)
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assign demux_select[1*INT_TLP_SEG_COUNT+n] = demux_match_tlp_hdr[n*128+121 +: 5] == 5'b00101;
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assign demux_select[0*INT_TLP_SEG_COUNT+n] = !demux_select[1*INT_TLP_SEG_COUNT+n];
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end
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endgenerate
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wire [TLP_SEG_COUNT*3-1:0] rx_cpl_tlp_bar_id;
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wire [TLP_SEG_COUNT*8-1:0] rx_cpl_tlp_func_num;
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pcie_tlp_demux #(
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.PORTS(2),
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.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
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.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
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.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
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.SEQ_NUM_WIDTH(1),
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.IN_TLP_SEG_COUNT(INT_TLP_SEG_COUNT),
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.OUT_TLP_SEG_COUNT(TLP_SEG_COUNT),
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.FIFO_ENABLE(1),
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.FIFO_DEPTH((1024/4)*2),
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.FIFO_WATERMARK((1024/4)*2-TLP_STRB_WIDTH*20)
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)
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pcie_tlp_demux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* TLP input
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*/
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.in_tlp_data(rx_tlp_data_reg),
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.in_tlp_strb(rx_tlp_strb_reg),
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.in_tlp_hdr(rx_tlp_hdr_reg),
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.in_tlp_seq(0),
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.in_tlp_bar_id(rx_tlp_bar_id_reg),
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.in_tlp_func_num(rx_tlp_func_num_reg),
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.in_tlp_error(0),
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.in_tlp_valid(rx_tlp_valid_reg),
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.in_tlp_sop(rx_tlp_sop_reg),
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.in_tlp_eop(rx_tlp_eop_reg),
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.in_tlp_ready(fifo_tlp_ready),
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/*
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* TLP output
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*/
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.out_tlp_data({rx_cpl_tlp_data, rx_req_tlp_data}),
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.out_tlp_strb({rx_cpl_tlp_strb, rx_req_tlp_strb}),
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.out_tlp_hdr({rx_cpl_tlp_hdr, rx_req_tlp_hdr}),
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.out_tlp_seq(),
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.out_tlp_bar_id({rx_cpl_tlp_bar_id, rx_req_tlp_bar_id}),
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.out_tlp_func_num({rx_cpl_tlp_func_num, rx_req_tlp_func_num}),
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.out_tlp_error(),
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.out_tlp_valid({rx_cpl_tlp_valid, rx_req_tlp_valid}),
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.out_tlp_sop({rx_cpl_tlp_sop, rx_req_tlp_sop}),
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.out_tlp_eop({rx_cpl_tlp_eop, rx_req_tlp_eop}),
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.out_tlp_ready({rx_cpl_tlp_ready, rx_req_tlp_ready}),
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/*
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* Fields
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*/
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.match_tlp_hdr(demux_match_tlp_hdr),
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.match_tlp_bar_id(),
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.match_tlp_func_num(),
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/*
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* Control
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*/
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.enable(1'b1),
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.drop(demux_drop),
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.select(demux_select),
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/*
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* Status
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*/
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.fifo_half_full(),
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.fifo_watermark(fifo_watermark)
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);
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assign rx_cpl_tlp_error = 0;
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integer seg, lane;
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reg valid;
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always @* begin
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rx_tlp_data_next = rx_tlp_data_reg;
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rx_tlp_strb_next = rx_tlp_strb_reg;
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rx_tlp_hdr_next = rx_tlp_hdr_reg;
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rx_tlp_bar_id_next = rx_tlp_bar_id_reg;
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rx_tlp_func_num_next = rx_tlp_func_num_reg;
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rx_tlp_valid_next = fifo_tlp_ready ? 0 : rx_tlp_valid_reg;
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rx_tlp_sop_next = rx_tlp_sop_reg;
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rx_tlp_eop_next = rx_tlp_eop_reg;
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tlp_hdr_4dw_next = tlp_hdr_4dw_reg;
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rx_st_data_int_next = rx_st_data_int_reg;
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rx_st_strb_int_next = rx_st_strb_int_reg;
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rx_st_sop_int_next = rx_st_sop_int_reg;
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rx_st_eop_int_next = rx_st_eop_int_reg;
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rx_st_valid_int_next = rx_st_valid_int_reg;
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rx_st_strb_sop_int_next = rx_st_strb_sop_int_reg;
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rx_st_strb_eop_int_next = rx_st_strb_eop_int_reg;
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rx_st_vf_active_int_next = rx_st_vf_active_int_reg;
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rx_st_func_num_int_next = rx_st_func_num_int_reg;
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rx_st_vf_num_int_next = rx_st_vf_num_int_reg;
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rx_st_bar_range_int_next = rx_st_bar_range_int_reg;
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// decode framing
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for (seg = 0; seg < SEG_COUNT; seg = seg + 1) begin
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rx_st_strb[SEG_STRB_WIDTH*seg +: SEG_STRB_WIDTH] = {SEG_STRB_WIDTH{1'b1}};
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rx_st_strb_sop[SEG_STRB_WIDTH*seg +: SEG_STRB_WIDTH] = rx_st_sop[seg];
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rx_st_strb_eop[SEG_STRB_WIDTH*seg +: SEG_STRB_WIDTH] = 0;
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if (rx_st_eop[seg]) begin
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rx_st_strb[SEG_STRB_WIDTH*seg +: SEG_STRB_WIDTH] = {SEG_STRB_WIDTH{1'b1}} >> rx_st_empty[SEG_EMPTY_WIDTH*seg +: SEG_EMPTY_WIDTH];
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rx_st_strb_eop[SEG_STRB_WIDTH*seg +: SEG_STRB_WIDTH] = {1'b1, {SEG_STRB_WIDTH-1{1'b0}}} >> rx_st_empty[SEG_EMPTY_WIDTH*seg +: SEG_EMPTY_WIDTH];
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end
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end
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for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
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// extract header
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tlp_hdr[128*seg+96 +: 32] = rx_st_data_full[SEG_DATA_WIDTH*seg+0 +: 32];
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tlp_hdr[128*seg+64 +: 32] = rx_st_data_full[SEG_DATA_WIDTH*seg+32 +: 32];
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tlp_hdr[128*seg+32 +: 32] = rx_st_data_full[SEG_DATA_WIDTH*seg+64 +: 32];
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tlp_hdr[128*seg+0 +: 32] = rx_st_data_full[SEG_DATA_WIDTH*seg+96 +: 32];
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case (rx_st_bar_range_full[3*seg +: 3])
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3'd6: tlp_bar_id[3*seg +: 3] = IO_BAR_INDEX; // IO BAR
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3'd7: tlp_bar_id[3*seg +: 3] = 6; // expansion ROM BAR
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default: tlp_bar_id[3*seg +: 3] = rx_st_bar_range_full[3*seg +: 3]; // memory BAR
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endcase
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tlp_func_num[8*seg +: 8] = rx_st_func_num_full[2*seg +: 2];
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end
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if (fifo_tlp_ready) begin
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rx_tlp_strb_next = 0;
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rx_tlp_valid_next = 0;
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rx_tlp_sop_next = 0;
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rx_tlp_eop_next = 0;
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for (seg = 0; seg < INT_TLP_SEG_COUNT; seg = seg + 1) begin
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if (rx_st_valid_full[seg]) begin
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if (rx_st_sop_full[seg]) begin
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rx_tlp_hdr_next[TLP_HDR_WIDTH*seg +: TLP_HDR_WIDTH] = tlp_hdr[128*seg +: 128];
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rx_tlp_bar_id_next[3*seg +: 3] = tlp_bar_id[3*seg +: 3];
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rx_tlp_func_num_next[8*seg +: 8] = tlp_func_num[8*seg +: 8];
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tlp_hdr_4dw_next = tlp_hdr[128*seg+125];
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end
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rx_tlp_sop_next[seg] = rx_st_sop_full[seg];
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rx_tlp_data_next[INT_TLP_SEG_DATA_WIDTH*seg +: INT_TLP_SEG_DATA_WIDTH] = rx_st_data_full >> (INT_TLP_SEG_DATA_WIDTH*seg + (32*(3+tlp_hdr_4dw_next)));
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if (rx_st_eop_full[seg]) begin
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rx_tlp_strb_next[INT_TLP_SEG_STRB_WIDTH*seg +: INT_TLP_SEG_STRB_WIDTH] = rx_st_strb_full[INT_TLP_SEG_STRB_WIDTH*seg +: INT_TLP_SEG_STRB_WIDTH] >> (3+tlp_hdr_4dw_next);
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if (rx_st_sop_full[seg] || rx_st_strb_eop_full[INT_TLP_SEG_STRB_WIDTH*seg +: INT_TLP_SEG_STRB_WIDTH] >> (3+tlp_hdr_4dw_next)) begin
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rx_tlp_eop_next[seg] = 1'b1;
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rx_tlp_valid_next[seg] = 1'b1;
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end
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rx_st_valid_int_next[seg] = 1'b0;
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end else begin
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rx_tlp_strb_next[INT_TLP_SEG_STRB_WIDTH*seg +: INT_TLP_SEG_STRB_WIDTH] = rx_st_strb_full >> ((3+tlp_hdr_4dw_next) + INT_TLP_SEG_STRB_WIDTH*seg);
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if (rx_st_valid_full[seg+1]) begin
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rx_tlp_eop_next[seg] = (rx_st_strb_eop_full[INT_TLP_SEG_STRB_WIDTH*(seg+1) +: INT_TLP_SEG_STRB_WIDTH] & (tlp_hdr_4dw_next ? 4'hF : 4'h7)) != 0;
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rx_tlp_valid_next[seg] = 1'b1;
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rx_st_valid_int_next[seg] = 1'b0;
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end
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end
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end
|
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end
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end
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|
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if (rx_st_valid) begin
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rx_st_data_int_next = rx_st_data;
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rx_st_strb_int_next = rx_st_strb;
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rx_st_sop_int_next = rx_st_sop;
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rx_st_eop_int_next = rx_st_eop;
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rx_st_valid_int_next = rx_st_valid;
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rx_st_strb_sop_int_next = rx_st_strb_sop;
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rx_st_strb_eop_int_next = rx_st_strb_eop;
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rx_st_vf_active_int_next = rx_st_vf_active;
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rx_st_func_num_int_next = rx_st_func_num;
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rx_st_vf_num_int_next = rx_st_vf_num;
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rx_st_bar_range_int_next = rx_st_bar_range;
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|
end
|
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end
|
|
|
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always @(posedge clk) begin
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rx_tlp_data_reg <= rx_tlp_data_next;
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rx_tlp_strb_reg <= rx_tlp_strb_next;
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rx_tlp_hdr_reg <= rx_tlp_hdr_next;
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rx_tlp_bar_id_reg <= rx_tlp_bar_id_next;
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rx_tlp_func_num_reg <= rx_tlp_func_num_next;
|
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rx_tlp_valid_reg <= rx_tlp_valid_next;
|
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rx_tlp_sop_reg <= rx_tlp_sop_next;
|
|
rx_tlp_eop_reg <= rx_tlp_eop_next;
|
|
tlp_hdr_4dw_reg <= tlp_hdr_4dw_next;
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|
|
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rx_st_data_int_reg <= rx_st_data_int_next;
|
|
rx_st_strb_int_reg <= rx_st_strb_int_next;
|
|
rx_st_sop_int_reg <= rx_st_sop_int_next;
|
|
rx_st_eop_int_reg <= rx_st_eop_int_next;
|
|
rx_st_valid_int_reg <= rx_st_valid_int_next;
|
|
rx_st_strb_sop_int_reg <= rx_st_strb_sop_int_next;
|
|
rx_st_strb_eop_int_reg <= rx_st_strb_eop_int_next;
|
|
rx_st_vf_active_int_reg <= rx_st_vf_active_int_next;
|
|
rx_st_func_num_int_reg <= rx_st_func_num_int_next;
|
|
rx_st_vf_num_int_reg <= rx_st_vf_num_int_next;
|
|
rx_st_bar_range_int_reg <= rx_st_bar_range_int_next;
|
|
|
|
if (rst) begin
|
|
rx_tlp_valid_reg <= 0;
|
|
|
|
rx_st_valid_int_reg <= 0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|