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215 lines
8.3 KiB
Verilog
215 lines
8.3 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Event mux
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*/
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module event_mux #
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(
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// Number of ports
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parameter PORTS = 2,
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// Queue index width
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parameter QUEUE_INDEX_WIDTH = 4,
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// Event type field width
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parameter EVENT_TYPE_WIDTH = 16,
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// Event source field width
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parameter EVENT_SOURCE_WIDTH = 16,
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// select round robin arbitration
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parameter ARB_TYPE_ROUND_ROBIN = 0,
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// LSB priority selection
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parameter ARB_LSB_HIGH_PRIORITY = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Event output
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*/
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output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_event_queue,
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output wire [EVENT_TYPE_WIDTH-1:0] m_axis_event_type,
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output wire [EVENT_SOURCE_WIDTH-1:0] m_axis_event_source,
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output wire m_axis_event_valid,
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input wire m_axis_event_ready,
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/*
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* Event input
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*/
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input wire [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_event_queue,
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input wire [PORTS*EVENT_TYPE_WIDTH-1:0] s_axis_event_type,
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input wire [PORTS*EVENT_SOURCE_WIDTH-1:0] s_axis_event_source,
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input wire [PORTS-1:0] s_axis_event_valid,
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output wire [PORTS-1:0] s_axis_event_ready
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);
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parameter CL_PORTS = $clog2(PORTS);
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// eventriptor mux
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wire [PORTS-1:0] request;
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wire [PORTS-1:0] acknowledge;
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wire [PORTS-1:0] grant;
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wire grant_valid;
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wire [CL_PORTS-1:0] grant_encoded;
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// internal datapath
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_event_queue_int;
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reg [EVENT_TYPE_WIDTH-1:0] m_axis_event_type_int;
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reg [EVENT_SOURCE_WIDTH-1:0] m_axis_event_source_int;
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reg m_axis_event_valid_int;
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reg m_axis_event_ready_int_reg = 1'b0;
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wire m_axis_event_ready_int_early;
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assign s_axis_event_ready = (m_axis_event_ready_int_reg && grant_valid) << grant_encoded;
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// mux for incoming packet
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wire [QUEUE_INDEX_WIDTH-1:0] current_s_event_queue = s_axis_event_queue[grant_encoded*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH];
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wire [EVENT_TYPE_WIDTH-1:0] current_s_event_type = s_axis_event_type[grant_encoded*EVENT_TYPE_WIDTH +: EVENT_TYPE_WIDTH];
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wire [EVENT_SOURCE_WIDTH-1:0] current_s_event_source = s_axis_event_source[grant_encoded*EVENT_SOURCE_WIDTH +: EVENT_SOURCE_WIDTH];
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wire current_s_event_valid = s_axis_event_valid[grant_encoded];
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wire current_s_event_ready = s_axis_event_ready[grant_encoded];
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// arbiter instance
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arbiter #(
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.PORTS(PORTS),
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.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
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.ARB_BLOCK(1),
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.ARB_BLOCK_ACK(1),
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.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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assign request = s_axis_event_valid & ~grant;
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assign acknowledge = grant & s_axis_event_valid & s_axis_event_ready;
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always @* begin
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m_axis_event_queue_int = current_s_event_queue;
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m_axis_event_type_int = current_s_event_type;
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m_axis_event_source_int = current_s_event_source;
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m_axis_event_valid_int = current_s_event_valid && m_axis_event_ready_int_reg && grant_valid;
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end
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// output datapath logic
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reg [QUEUE_INDEX_WIDTH-1:0] m_axis_event_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
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reg [EVENT_TYPE_WIDTH-1:0] m_axis_event_type_reg = {EVENT_TYPE_WIDTH{1'b0}};
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reg [EVENT_SOURCE_WIDTH-1:0] m_axis_event_source_reg = {EVENT_SOURCE_WIDTH{1'b0}};
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reg m_axis_event_valid_reg = 1'b0, m_axis_event_valid_next;
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reg [QUEUE_INDEX_WIDTH-1:0] temp_m_axis_event_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
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reg [EVENT_TYPE_WIDTH-1:0] temp_m_axis_event_type_reg = {EVENT_TYPE_WIDTH{1'b0}};
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reg [EVENT_SOURCE_WIDTH-1:0] temp_m_axis_event_source_reg = {EVENT_SOURCE_WIDTH{1'b0}};
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reg temp_m_axis_event_valid_reg = 1'b0, temp_m_axis_event_valid_next;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_event_queue = m_axis_event_queue_reg;
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assign m_axis_event_type = m_axis_event_type_reg;
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assign m_axis_event_source = m_axis_event_source_reg;
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assign m_axis_event_valid = m_axis_event_valid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_event_ready_int_early = m_axis_event_ready || (!temp_m_axis_event_valid_reg && (!m_axis_event_valid_reg || !m_axis_event_valid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_event_valid_next = m_axis_event_valid_reg;
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temp_m_axis_event_valid_next = temp_m_axis_event_valid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_event_ready_int_reg) begin
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// input is ready
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if (m_axis_event_ready || !m_axis_event_valid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_event_valid_next = m_axis_event_valid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_event_valid_next = m_axis_event_valid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_event_ready) begin
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// input is not ready, but output is ready
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m_axis_event_valid_next = temp_m_axis_event_valid_reg;
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temp_m_axis_event_valid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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m_axis_event_valid_reg <= 1'b0;
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m_axis_event_ready_int_reg <= 1'b0;
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temp_m_axis_event_valid_reg <= 1'b0;
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end else begin
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m_axis_event_valid_reg <= m_axis_event_valid_next;
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m_axis_event_ready_int_reg <= m_axis_event_ready_int_early;
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temp_m_axis_event_valid_reg <= temp_m_axis_event_valid_next;
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end
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// datapath
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if (store_axis_int_to_output) begin
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m_axis_event_queue_reg <= m_axis_event_queue_int;
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m_axis_event_type_reg <= m_axis_event_type_int;
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m_axis_event_source_reg <= m_axis_event_source_int;
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end else if (store_axis_temp_to_output) begin
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m_axis_event_queue_reg <= temp_m_axis_event_queue_reg;
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m_axis_event_type_reg <= temp_m_axis_event_type_reg;
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m_axis_event_source_reg <= temp_m_axis_event_source_reg;
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end
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if (store_axis_int_to_temp) begin
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temp_m_axis_event_queue_reg <= m_axis_event_queue_int;
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temp_m_axis_event_type_reg <= m_axis_event_type_int;
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temp_m_axis_event_source_reg <= m_axis_event_source_int;
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end
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end
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endmodule
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