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225 lines
7.0 KiB
Verilog
225 lines
7.0 KiB
Verilog
/*
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Copyright (c) 2014-2015 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream asynchronous FIFO
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*/
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module axis_async_fifo #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 8
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)
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(
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/*
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* Common asynchronous reset
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*/
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input wire async_rst,
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/*
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* AXI input
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*/
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input wire input_clk,
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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input wire output_clk,
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
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reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next;
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reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
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reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next;
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reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}};
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reg input_rst_sync1_reg = 1'b1;
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reg input_rst_sync2_reg = 1'b1;
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reg input_rst_sync3_reg = 1'b1;
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reg output_rst_sync1_reg = 1'b1;
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reg output_rst_sync2_reg = 1'b1;
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reg output_rst_sync3_reg = 1'b1;
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reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
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reg output_axis_tlast_reg = 1'b0;
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reg output_axis_tuser_reg = 1'b0;
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// full when first TWO MSBs do NOT match, but rest matches
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// (gray code equivalent of first MSB different but rest same)
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wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) &&
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(wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) &&
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(wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0]));
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// empty when pointers match exactly
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wire empty = rd_ptr_gray_reg == wr_ptr_gray_sync2_reg;
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// control signals
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reg write;
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reg read;
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assign input_axis_tready = ~full & ~input_rst_sync3_reg;
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assign output_axis_tdata = output_axis_tdata_reg;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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assign output_axis_tlast = output_axis_tlast_reg;
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assign output_axis_tuser = output_axis_tuser_reg;
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// reset synchronization
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always @(posedge input_clk or posedge async_rst) begin
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if (async_rst) begin
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input_rst_sync1_reg <= 1'b1;
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input_rst_sync2_reg <= 1'b1;
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input_rst_sync3_reg <= 1'b1;
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end else begin
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input_rst_sync1_reg <= 1'b0;
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input_rst_sync2_reg <= input_rst_sync1_reg | output_rst_sync1_reg;
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input_rst_sync3_reg <= input_rst_sync2_reg;
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end
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end
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always @(posedge output_clk or posedge async_rst) begin
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if (async_rst) begin
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output_rst_sync1_reg <= 1'b1;
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output_rst_sync2_reg <= 1'b1;
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output_rst_sync3_reg <= 1'b1;
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end else begin
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output_rst_sync1_reg <= 1'b0;
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output_rst_sync2_reg <= output_rst_sync1_reg;
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output_rst_sync3_reg <= output_rst_sync2_reg;
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end
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end
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// Write logic
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always @* begin
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write = 1'b0;
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wr_ptr_next = wr_ptr_reg;
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wr_ptr_gray_next = wr_ptr_gray_reg;
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if (input_axis_tvalid) begin
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// input data valid
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if (~full) begin
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// not full, perform write
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write = 1'b1;
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wr_ptr_next = wr_ptr_reg + 1;
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wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1);
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end
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end
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end
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always @(posedge input_clk) begin
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if (input_rst_sync3_reg) begin
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wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
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end else begin
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wr_ptr_reg <= wr_ptr_next;
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wr_ptr_gray_reg <= wr_ptr_gray_next;
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end
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if (write) begin
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mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
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end
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end
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// pointer synchronization
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always @(posedge input_clk) begin
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if (input_rst_sync3_reg) begin
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rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
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rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
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end else begin
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rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg;
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rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg;
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end
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end
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always @(posedge output_clk) begin
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if (output_rst_sync3_reg) begin
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wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}};
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wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}};
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end else begin
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wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg;
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wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg;
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end
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end
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// Read logic
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always @* begin
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read = 1'b0;
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rd_ptr_next = rd_ptr_reg;
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rd_ptr_gray_next = rd_ptr_gray_reg;
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output_axis_tvalid_next = output_axis_tvalid_reg;
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if (output_axis_tready | ~output_axis_tvalid) begin
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// output data not valid OR currently being transferred
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if (~empty) begin
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// not empty, perform read
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read = 1'b1;
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output_axis_tvalid_next = 1'b1;
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rd_ptr_next = rd_ptr_reg + 1;
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rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1);
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end else begin
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output_axis_tvalid_next = 1'b0;
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end
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end
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end
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always @(posedge output_clk) begin
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if (output_rst_sync3_reg) begin
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rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
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rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}};
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output_axis_tvalid_reg <= 1'b0;
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end else begin
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rd_ptr_reg <= rd_ptr_next;
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rd_ptr_gray_reg <= rd_ptr_gray_next;
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output_axis_tvalid_reg <= output_axis_tvalid_next;
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end
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if (read) begin
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{output_axis_tlast_reg, output_axis_tuser_reg, output_axis_tdata_reg} <= mem[rd_ptr_reg[ADDR_WIDTH-1:0]];
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end
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end
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endmodule
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