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152 lines
3.5 KiB
Verilog
152 lines
3.5 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Generic source synchronous DDR input
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*/
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module ssio_ddr_in #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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parameter TARGET = "GENERIC",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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parameter IODDR_STYLE = "IODDR2",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-6, 7-series
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// Use BUFG for Virtex-5, Spartan-6, Ultrascale
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parameter CLOCK_INPUT_STYLE = "BUFG",
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// Width of register in bits
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parameter WIDTH = 1
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)
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(
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input wire input_clk,
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input wire [WIDTH-1:0] input_d,
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output wire output_clk,
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output wire [WIDTH-1:0] output_q1,
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output wire [WIDTH-1:0] output_q2
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);
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wire clk_int;
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wire clk_io;
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generate
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if (TARGET == "XILINX") begin
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// use Xilinx clocking primitives
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if (CLOCK_INPUT_STYLE == "BUFG") begin
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// buffer RX clock
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BUFG
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clk_bufg (
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.I(input_clk),
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.O(clk_int)
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);
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// pass through RX clock to logic and input buffers
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assign clk_io = clk_int;
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assign output_clk = clk_int;
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end else if (CLOCK_INPUT_STYLE == "BUFR") begin
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assign clk_int = input_clk;
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// pass through RX clock to input buffers
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BUFIO
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clk_bufio (
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.I(clk_int),
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.O(clk_io)
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);
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// pass through RX clock to logic
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BUFR #(
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.BUFR_DIVIDE("BYPASS")
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)
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clk_bufr (
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.I(clk_int),
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.O(output_clk),
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.CE(1'b1),
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.CLR(1'b0)
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);
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end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
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assign clk_int = input_clk;
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// pass through RX clock to input buffers
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BUFIO
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clk_bufio (
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.I(clk_int),
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.O(clk_io)
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);
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// pass through RX clock to MAC
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BUFG
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clk_bufg (
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.I(clk_int),
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.O(output_clk)
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);
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end
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end else begin
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// pass through RX clock to input buffers
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assign clk_io = input_clk;
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// pass through RX clock to logic
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assign clk_int = input_clk;
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assign output_clk = clk_int;
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end
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endgenerate
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iddr #(
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.TARGET(TARGET),
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.IODDR_STYLE(IODDR_STYLE),
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.WIDTH(WIDTH)
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)
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data_iddr_inst (
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.clk(clk_io),
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.d(input_d),
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.q1(output_q1),
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.q2(output_q2)
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);
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endmodule
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`resetall
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