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218 lines
8.0 KiB
Verilog
218 lines
8.0 KiB
Verilog
/*
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Copyright (c) 2019-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* DMA interface mux (write)
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*/
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module dma_if_mux_wr #
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(
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// Number of ports
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parameter PORTS = 2,
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// RAM segment count
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parameter SEG_COUNT = 2,
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// RAM segment data width
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parameter SEG_DATA_WIDTH = 64,
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// RAM segment address width
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parameter SEG_ADDR_WIDTH = 8,
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// RAM segment byte enable width
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parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
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// Input RAM segment select width
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parameter S_RAM_SEL_WIDTH = 2,
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// Output RAM segment select width
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// Additional bits required for response routing
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parameter M_RAM_SEL_WIDTH = S_RAM_SEL_WIDTH+$clog2(PORTS),
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// RAM address width
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parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
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// DMA address width
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parameter DMA_ADDR_WIDTH = 64,
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// Length field width
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parameter LEN_WIDTH = 16,
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// Input tag field width
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parameter S_TAG_WIDTH = 8,
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// Output tag field width (towards DMA module)
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// Additional bits required for response routing
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parameter M_TAG_WIDTH = S_TAG_WIDTH+$clog2(PORTS),
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// select round robin arbitration
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parameter ARB_TYPE_ROUND_ROBIN = 0,
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// LSB priority selection
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parameter ARB_LSB_HIGH_PRIORITY = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Write descriptor output (to DMA interface)
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*/
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output wire [DMA_ADDR_WIDTH-1:0] m_axis_write_desc_dma_addr,
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output wire [M_RAM_SEL_WIDTH-1:0] m_axis_write_desc_ram_sel,
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output wire [RAM_ADDR_WIDTH-1:0] m_axis_write_desc_ram_addr,
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output wire [LEN_WIDTH-1:0] m_axis_write_desc_len,
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output wire [M_TAG_WIDTH-1:0] m_axis_write_desc_tag,
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output wire m_axis_write_desc_valid,
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input wire m_axis_write_desc_ready,
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/*
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* Write descriptor status input (from DMA interface)
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*/
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input wire [M_TAG_WIDTH-1:0] s_axis_write_desc_status_tag,
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input wire [3:0] s_axis_write_desc_status_error,
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input wire s_axis_write_desc_status_valid,
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/*
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* Write descriptor input
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*/
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input wire [PORTS*DMA_ADDR_WIDTH-1:0] s_axis_write_desc_dma_addr,
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input wire [PORTS*S_RAM_SEL_WIDTH-1:0] s_axis_write_desc_ram_sel,
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input wire [PORTS*RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
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input wire [PORTS*LEN_WIDTH-1:0] s_axis_write_desc_len,
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input wire [PORTS*S_TAG_WIDTH-1:0] s_axis_write_desc_tag,
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input wire [PORTS-1:0] s_axis_write_desc_valid,
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output wire [PORTS-1:0] s_axis_write_desc_ready,
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/*
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* Write descriptor status output
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*/
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output wire [PORTS*S_TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
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output wire [PORTS*4-1:0] m_axis_write_desc_status_error,
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output wire [PORTS-1:0] m_axis_write_desc_status_valid,
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/*
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* RAM interface (from DMA interface)
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*/
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input wire [SEG_COUNT*M_RAM_SEL_WIDTH-1:0] if_ram_rd_cmd_sel,
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input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] if_ram_rd_cmd_addr,
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input wire [SEG_COUNT-1:0] if_ram_rd_cmd_valid,
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output wire [SEG_COUNT-1:0] if_ram_rd_cmd_ready,
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output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] if_ram_rd_resp_data,
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output wire [SEG_COUNT-1:0] if_ram_rd_resp_valid,
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input wire [SEG_COUNT-1:0] if_ram_rd_resp_ready,
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/*
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* RAM interface (towards RAM)
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*/
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output wire [PORTS*SEG_COUNT*S_RAM_SEL_WIDTH-1:0] ram_rd_cmd_sel,
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output wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr,
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output wire [PORTS*SEG_COUNT-1:0] ram_rd_cmd_valid,
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input wire [PORTS*SEG_COUNT-1:0] ram_rd_cmd_ready,
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input wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_rd_resp_data,
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input wire [PORTS*SEG_COUNT-1:0] ram_rd_resp_valid,
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output wire [PORTS*SEG_COUNT-1:0] ram_rd_resp_ready
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);
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dma_if_desc_mux #(
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.PORTS(PORTS),
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.EXTEND_RAM_SEL(1),
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.S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
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.M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH),
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.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
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.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.S_TAG_WIDTH(S_TAG_WIDTH),
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.M_TAG_WIDTH(M_TAG_WIDTH),
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.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
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.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
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)
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dma_if_desc_mux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Read descriptor output (to DMA interface)
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*/
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.m_axis_desc_dma_addr(m_axis_write_desc_dma_addr),
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.m_axis_desc_ram_sel(m_axis_write_desc_ram_sel),
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.m_axis_desc_ram_addr(m_axis_write_desc_ram_addr),
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.m_axis_desc_len(m_axis_write_desc_len),
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.m_axis_desc_tag(m_axis_write_desc_tag),
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.m_axis_desc_valid(m_axis_write_desc_valid),
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.m_axis_desc_ready(m_axis_write_desc_ready),
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/*
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* Read descriptor status input (from DMA interface)
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*/
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.s_axis_desc_status_tag(s_axis_write_desc_status_tag),
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.s_axis_desc_status_error(s_axis_write_desc_status_error),
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.s_axis_desc_status_valid(s_axis_write_desc_status_valid),
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/*
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* Read descriptor input
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*/
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.s_axis_desc_dma_addr(s_axis_write_desc_dma_addr),
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.s_axis_desc_ram_sel(s_axis_write_desc_ram_sel),
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.s_axis_desc_ram_addr(s_axis_write_desc_ram_addr),
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.s_axis_desc_len(s_axis_write_desc_len),
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.s_axis_desc_tag(s_axis_write_desc_tag),
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.s_axis_desc_valid(s_axis_write_desc_valid),
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.s_axis_desc_ready(s_axis_write_desc_ready),
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/*
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* Read descriptor status output
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*/
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.m_axis_desc_status_tag(m_axis_write_desc_status_tag),
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.m_axis_desc_status_error(m_axis_write_desc_status_error),
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.m_axis_desc_status_valid(m_axis_write_desc_status_valid)
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);
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dma_ram_demux_rd #(
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.PORTS(PORTS),
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.SEG_COUNT(SEG_COUNT),
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.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
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.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
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.S_RAM_SEL_WIDTH(S_RAM_SEL_WIDTH),
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.M_RAM_SEL_WIDTH(M_RAM_SEL_WIDTH)
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)
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dma_ram_demux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* RAM interface (from DMA client/interface)
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*/
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.ctrl_rd_cmd_sel(if_ram_rd_cmd_sel),
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.ctrl_rd_cmd_addr(if_ram_rd_cmd_addr),
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.ctrl_rd_cmd_valid(if_ram_rd_cmd_valid),
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.ctrl_rd_cmd_ready(if_ram_rd_cmd_ready),
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.ctrl_rd_resp_data(if_ram_rd_resp_data),
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.ctrl_rd_resp_valid(if_ram_rd_resp_valid),
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.ctrl_rd_resp_ready(if_ram_rd_resp_ready),
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/*
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* RAM interface (towards RAM)
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*/
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.ram_rd_cmd_sel(ram_rd_cmd_sel),
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.ram_rd_cmd_addr(ram_rd_cmd_addr),
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.ram_rd_cmd_valid(ram_rd_cmd_valid),
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.ram_rd_cmd_ready(ram_rd_cmd_ready),
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.ram_rd_resp_data(ram_rd_resp_data),
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.ram_rd_resp_valid(ram_rd_resp_valid),
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.ram_rd_resp_ready(ram_rd_resp_ready)
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);
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endmodule
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