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98 lines
2.7 KiB
Verilog
98 lines
2.7 KiB
Verilog
/*
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Copyright 2019, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for rx_checksum
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*/
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module test_rx_checksum;
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// Parameters
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parameter DATA_WIDTH = 256;
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parameter KEEP_WIDTH = (DATA_WIDTH/8);
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
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reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
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reg s_axis_tvalid = 0;
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reg s_axis_tlast = 0;
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// Outputs
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wire [15:0] m_axis_csum;
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wire m_axis_csum_valid;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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s_axis_tdata,
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s_axis_tkeep,
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s_axis_tvalid,
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s_axis_tlast
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);
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$to_myhdl(
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m_axis_csum,
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m_axis_csum_valid
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);
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// dump file
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$dumpfile("test_rx_checksum.lxt");
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$dumpvars(0, test_rx_checksum);
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end
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rx_checksum #(
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.DATA_WIDTH(DATA_WIDTH),
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.KEEP_WIDTH(KEEP_WIDTH)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tlast(s_axis_tlast),
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.m_axis_csum(m_axis_csum),
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.m_axis_csum_valid(m_axis_csum_valid)
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);
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endmodule
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