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142 lines
3.1 KiB
C
142 lines
3.1 KiB
C
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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#include "mqnic.h"
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struct mqnic_cq *mqnic_create_cq(struct mqnic_if *interface)
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{
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struct mqnic_cq *cq;
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cq = kzalloc(sizeof(*cq), GFP_KERNEL);
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if (!cq)
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return ERR_PTR(-ENOMEM);
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cq->dev = interface->dev;
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cq->interface = interface;
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cq->cqn = -1;
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cq->enabled = 0;
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cq->hw_addr = NULL;
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cq->prod_ptr = 0;
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cq->cons_ptr = 0;
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return cq;
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}
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void mqnic_destroy_cq(struct mqnic_cq *cq)
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{
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mqnic_close_cq(cq);
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kfree(cq);
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}
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int mqnic_open_cq(struct mqnic_cq *cq, struct mqnic_eq *eq, int size)
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{
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int ret;
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if (cq->enabled || cq->hw_addr || cq->buf || !eq)
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return -EINVAL;
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cq->cqn = mqnic_res_alloc(cq->interface->cq_res);
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if (cq->cqn < 0)
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return -ENOMEM;
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cq->size = roundup_pow_of_two(size);
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cq->size_mask = cq->size - 1;
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cq->stride = roundup_pow_of_two(MQNIC_CPL_SIZE);
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cq->buf_size = cq->size * cq->stride;
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cq->buf = dma_alloc_coherent(cq->dev, cq->buf_size, &cq->buf_dma_addr, GFP_KERNEL);
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if (!cq->buf) {
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ret = -ENOMEM;
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goto fail;
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}
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cq->eq = eq;
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mqnic_eq_attach_cq(eq, cq);
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cq->hw_addr = mqnic_res_get_addr(cq->interface->cq_res, cq->cqn);
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cq->prod_ptr = 0;
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cq->cons_ptr = 0;
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memset(cq->buf, 1, cq->buf_size);
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// deactivate queue
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iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 0, cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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// set base address
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iowrite32((cq->buf_dma_addr & 0xfffff000),
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cq->hw_addr + MQNIC_CQ_BASE_ADDR_VF_REG + 0);
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iowrite32(cq->buf_dma_addr >> 32,
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cq->hw_addr + MQNIC_CQ_BASE_ADDR_VF_REG + 4);
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// set size
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iowrite32(MQNIC_CQ_CMD_SET_SIZE | ilog2(cq->size),
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cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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// set EQN
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iowrite32(MQNIC_CQ_CMD_SET_EQN | cq->eq->eqn,
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cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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// set pointers
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iowrite32(MQNIC_CQ_CMD_SET_PROD_PTR | (cq->prod_ptr & MQNIC_CQ_PTR_MASK),
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cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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iowrite32(MQNIC_CQ_CMD_SET_CONS_PTR | (cq->cons_ptr & MQNIC_CQ_PTR_MASK),
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cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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// activate queue
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iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 1, cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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cq->enabled = 1;
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return 0;
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fail:
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mqnic_close_eq(eq);
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return ret;
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}
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void mqnic_close_cq(struct mqnic_cq *cq)
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{
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if (cq->hw_addr) {
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// deactivate queue
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iowrite32(MQNIC_CQ_CMD_SET_ENABLE | 0, cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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}
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if (cq->eq) {
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mqnic_eq_detach_cq(cq->eq, cq);
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cq->eq = NULL;
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}
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cq->hw_addr = NULL;
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if (cq->buf) {
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dma_free_coherent(cq->dev, cq->buf_size, cq->buf, cq->buf_dma_addr);
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cq->buf = NULL;
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cq->buf_dma_addr = 0;
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}
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mqnic_res_free(cq->interface->cq_res, cq->cqn);
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cq->cqn = -1;
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cq->enabled = 0;
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}
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void mqnic_cq_read_prod_ptr(struct mqnic_cq *cq)
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{
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cq->prod_ptr += ((ioread32(cq->hw_addr + MQNIC_CQ_PTR_REG) >> 16) - cq->prod_ptr) & MQNIC_CQ_PTR_MASK;
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}
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void mqnic_cq_write_cons_ptr(struct mqnic_cq *cq)
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{
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iowrite32(MQNIC_CQ_CMD_SET_CONS_PTR | (cq->cons_ptr & MQNIC_CQ_PTR_MASK),
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cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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}
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void mqnic_arm_cq(struct mqnic_cq *cq)
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{
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if (!cq->enabled)
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return;
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iowrite32(MQNIC_CQ_CMD_SET_ARM | 1, cq->hw_addr + MQNIC_CQ_CTRL_STATUS_REG);
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}
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