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346 lines
13 KiB
C
346 lines
13 KiB
C
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright 2021, The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of The Regents of the
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* University of California.
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*/
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#include "mqnic.h"
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int mqnic_create_interface(struct mqnic_dev *mdev, struct mqnic_if **interface_ptr,
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int index, u8 __iomem *hw_addr)
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{
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struct device *dev = mdev->dev;
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struct mqnic_if *interface;
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struct reg_block *rb;
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int ret = 0;
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int k;
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u32 desc_block_size;
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interface = kzalloc(sizeof(*interface), GFP_KERNEL);
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if (!interface)
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return -ENOMEM;
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interface->mdev = mdev;
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interface->dev = dev;
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interface->index = index;
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interface->hw_regs_size = mdev->if_stride;
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interface->hw_addr = hw_addr;
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interface->csr_hw_addr = hw_addr + mdev->if_csr_offset;
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// Enumerate registers
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interface->rb_list = enumerate_reg_block_list(interface->hw_addr, mdev->if_csr_offset, interface->hw_regs_size);
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if (!interface->rb_list) {
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ret = -EIO;
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dev_err(dev, "Failed to enumerate blocks");
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goto fail;
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}
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dev_info(dev, "Interface-level register blocks:");
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for (rb = interface->rb_list; rb->type && rb->version; rb++)
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dev_info(dev, " type 0x%08x (v %d.%d.%d.%d)", rb->type, rb->version >> 24,
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(rb->version >> 16) & 0xff, (rb->version >> 8) & 0xff, rb->version & 0xff);
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interface->if_ctrl_rb = find_reg_block(interface->rb_list, MQNIC_RB_IF_CTRL_TYPE, MQNIC_RB_IF_CTRL_VER, 0);
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if (!interface->if_ctrl_rb) {
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ret = -EIO;
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dev_err(dev, "Interface control block not found");
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goto fail;
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}
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interface->if_features = ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_FEATURES);
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interface->max_tx_mtu = ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_MAX_TX_MTU);
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interface->max_rx_mtu = ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_MAX_RX_MTU);
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dev_info(dev, "IF features: 0x%08x", interface->if_features);
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dev_info(dev, "Max TX MTU: %d", interface->max_tx_mtu);
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dev_info(dev, "Max RX MTU: %d", interface->max_rx_mtu);
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interface->event_queue_rb = find_reg_block(interface->rb_list, MQNIC_RB_EVENT_QM_TYPE, MQNIC_RB_EVENT_QM_VER, 0);
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if (!interface->event_queue_rb) {
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ret = -EIO;
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dev_err(dev, "Event queue block not found");
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goto fail;
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}
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interface->event_queue_offset = ioread32(interface->event_queue_rb->regs + MQNIC_RB_EVENT_QM_REG_OFFSET);
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interface->event_queue_count = ioread32(interface->event_queue_rb->regs + MQNIC_RB_EVENT_QM_REG_COUNT);
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interface->event_queue_stride = ioread32(interface->event_queue_rb->regs + MQNIC_RB_EVENT_QM_REG_STRIDE);
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dev_info(dev, "Event queue offset: 0x%08x", interface->event_queue_offset);
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dev_info(dev, "Event queue count: %d", interface->event_queue_count);
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dev_info(dev, "Event queue stride: 0x%08x", interface->event_queue_stride);
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interface->event_queue_count = min_t(u32, interface->event_queue_count, MQNIC_MAX_EVENT_RINGS);
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interface->tx_queue_rb = find_reg_block(interface->rb_list, MQNIC_RB_TX_QM_TYPE, MQNIC_RB_TX_QM_VER, 0);
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if (!interface->tx_queue_rb) {
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ret = -EIO;
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dev_err(dev, "TX queue block not found");
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goto fail;
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}
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interface->tx_queue_offset = ioread32(interface->tx_queue_rb->regs + MQNIC_RB_TX_QM_REG_OFFSET);
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interface->tx_queue_count = ioread32(interface->tx_queue_rb->regs + MQNIC_RB_TX_QM_REG_COUNT);
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interface->tx_queue_stride = ioread32(interface->tx_queue_rb->regs + MQNIC_RB_TX_QM_REG_STRIDE);
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dev_info(dev, "TX queue offset: 0x%08x", interface->tx_queue_offset);
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dev_info(dev, "TX queue count: %d", interface->tx_queue_count);
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dev_info(dev, "TX queue stride: 0x%08x", interface->tx_queue_stride);
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interface->tx_queue_count = min_t(u32, interface->tx_queue_count, MQNIC_MAX_TX_RINGS);
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interface->tx_cpl_queue_rb = find_reg_block(interface->rb_list, MQNIC_RB_TX_CQM_TYPE, MQNIC_RB_TX_CQM_VER, 0);
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if (!interface->tx_cpl_queue_rb) {
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ret = -EIO;
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dev_err(dev, "TX completion queue block not found");
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goto fail;
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}
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interface->tx_cpl_queue_offset = ioread32(interface->tx_cpl_queue_rb->regs + MQNIC_RB_TX_CQM_REG_OFFSET);
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interface->tx_cpl_queue_count = ioread32(interface->tx_cpl_queue_rb->regs + MQNIC_RB_TX_CQM_REG_COUNT);
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interface->tx_cpl_queue_stride = ioread32(interface->tx_cpl_queue_rb->regs + MQNIC_RB_TX_CQM_REG_STRIDE);
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dev_info(dev, "TX completion queue offset: 0x%08x", interface->tx_cpl_queue_offset);
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dev_info(dev, "TX completion queue count: %d", interface->tx_cpl_queue_count);
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dev_info(dev, "TX completion queue stride: 0x%08x", interface->tx_cpl_queue_stride);
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interface->tx_cpl_queue_count = min_t(u32, interface->tx_cpl_queue_count, MQNIC_MAX_TX_CPL_RINGS);
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interface->rx_queue_rb = find_reg_block(interface->rb_list, MQNIC_RB_RX_QM_TYPE, MQNIC_RB_RX_QM_VER, 0);
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if (!interface->rx_queue_rb) {
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ret = -EIO;
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dev_err(dev, "RX queue block not found");
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goto fail;
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}
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interface->rx_queue_offset = ioread32(interface->rx_queue_rb->regs + MQNIC_RB_RX_QM_REG_OFFSET);
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interface->rx_queue_count = ioread32(interface->rx_queue_rb->regs + MQNIC_RB_RX_QM_REG_COUNT);
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interface->rx_queue_stride = ioread32(interface->rx_queue_rb->regs + MQNIC_RB_RX_QM_REG_STRIDE);
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dev_info(dev, "RX queue offset: 0x%08x", interface->rx_queue_offset);
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dev_info(dev, "RX queue count: %d", interface->rx_queue_count);
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dev_info(dev, "RX queue stride: 0x%08x", interface->rx_queue_stride);
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interface->rx_queue_count = min_t(u32, interface->rx_queue_count, MQNIC_MAX_RX_RINGS);
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interface->rx_cpl_queue_rb = find_reg_block(interface->rb_list, MQNIC_RB_RX_CQM_TYPE, MQNIC_RB_RX_CQM_VER, 0);
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if (!interface->rx_cpl_queue_rb) {
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ret = -EIO;
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dev_err(dev, "RX completion queue block not found");
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goto fail;
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}
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interface->rx_cpl_queue_offset = ioread32(interface->rx_cpl_queue_rb->regs + MQNIC_RB_RX_CQM_REG_OFFSET);
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interface->rx_cpl_queue_count = ioread32(interface->rx_cpl_queue_rb->regs + MQNIC_RB_RX_CQM_REG_COUNT);
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interface->rx_cpl_queue_stride = ioread32(interface->rx_cpl_queue_rb->regs + MQNIC_RB_RX_CQM_REG_STRIDE);
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dev_info(dev, "RX completion queue offset: 0x%08x", interface->rx_cpl_queue_offset);
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dev_info(dev, "RX completion queue count: %d", interface->rx_cpl_queue_count);
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dev_info(dev, "RX completion queue stride: 0x%08x", interface->rx_cpl_queue_stride);
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interface->rx_cpl_queue_count = min_t(u32, interface->rx_cpl_queue_count, MQNIC_MAX_RX_CPL_RINGS);
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// determine desc block size
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iowrite32(0xf << 8, hw_addr + interface->tx_queue_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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interface->max_desc_block_size = 1 << ((ioread32(hw_addr + interface->tx_queue_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG) >> 8) & 0xf);
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iowrite32(0, hw_addr + interface->tx_queue_offset + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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dev_info(dev, "Max desc block size: %d", interface->max_desc_block_size);
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interface->max_desc_block_size = min_t(u32, interface->max_desc_block_size, MQNIC_MAX_FRAGS);
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desc_block_size = min_t(u32, interface->max_desc_block_size, 4);
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*interface_ptr = interface;
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// create rings
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for (k = 0; k < interface->event_queue_count; k++) {
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ret = mqnic_create_eq_ring(interface, &interface->event_ring[k], k,
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hw_addr + interface->event_queue_offset + k * interface->event_queue_stride);
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if (ret)
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goto fail;
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ret = mqnic_alloc_eq_ring(interface->event_ring[k], mqnic_num_ev_queue_entries,
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MQNIC_EVENT_SIZE);
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if (ret)
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goto fail;
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mqnic_activate_eq_ring(interface->event_ring[k], mdev->irq[k % mdev->irq_count]);
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mqnic_arm_eq(interface->event_ring[k]);
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}
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for (k = 0; k < interface->tx_queue_count; k++) {
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ret = mqnic_create_tx_ring(interface, &interface->tx_ring[k], k,
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hw_addr + interface->tx_queue_offset + k * interface->tx_queue_stride);
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if (ret)
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goto fail;
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}
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for (k = 0; k < interface->tx_cpl_queue_count; k++) {
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ret = mqnic_create_cq_ring(interface, &interface->tx_cpl_ring[k], k,
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hw_addr + interface->tx_cpl_queue_offset + k * interface->tx_cpl_queue_stride);
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if (ret)
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goto fail;
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}
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for (k = 0; k < interface->rx_queue_count; k++) {
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ret = mqnic_create_rx_ring(interface, &interface->rx_ring[k], k,
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hw_addr + interface->rx_queue_offset + k * interface->rx_queue_stride);
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if (ret)
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goto fail;
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}
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for (k = 0; k < interface->rx_cpl_queue_count; k++) {
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ret = mqnic_create_cq_ring(interface, &interface->rx_cpl_ring[k], k,
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hw_addr + interface->rx_cpl_queue_offset + k * interface->rx_cpl_queue_stride);
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if (ret)
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goto fail;
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}
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// create ports
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interface->port_count = 0;
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while (interface->port_count < MQNIC_MAX_PORTS)
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{
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struct reg_block *sched_block_rb = find_reg_block(interface->rb_list, MQNIC_RB_SCHED_BLOCK_TYPE, MQNIC_RB_SCHED_BLOCK_VER, interface->port_count);
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if (!sched_block_rb)
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break;
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ret = mqnic_create_port(interface, &interface->port[interface->port_count],
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interface->port_count, sched_block_rb);
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if (ret)
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goto fail;
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interface->port_count++;
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}
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dev_info(dev, "Port count: %d", interface->port_count);
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// create net_devices
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interface->dev_port_base = mdev->dev_port_max;
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interface->dev_port_max = mdev->dev_port_max;
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interface->ndev_count = 1;
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for (k = 0; k < interface->ndev_count; k++) {
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ret = mqnic_create_netdev(interface, &interface->ndev[k], k, interface->dev_port_max++);
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if (ret)
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goto fail;
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}
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return 0;
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fail:
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mqnic_destroy_interface(interface_ptr);
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return ret;
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}
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void mqnic_destroy_interface(struct mqnic_if **interface_ptr)
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{
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struct mqnic_if *interface = *interface_ptr;
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int k;
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// destroy associated net_devices
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for (k = 0; k < ARRAY_SIZE(interface->ndev); k++)
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if (interface->ndev[k])
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mqnic_destroy_netdev(&interface->ndev[k]);
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// free rings
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for (k = 0; k < ARRAY_SIZE(interface->event_ring); k++)
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if (interface->event_ring[k])
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mqnic_destroy_eq_ring(&interface->event_ring[k]);
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for (k = 0; k < ARRAY_SIZE(interface->tx_ring); k++)
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if (interface->tx_ring[k])
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mqnic_destroy_tx_ring(&interface->tx_ring[k]);
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for (k = 0; k < ARRAY_SIZE(interface->tx_cpl_ring); k++)
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if (interface->tx_cpl_ring[k])
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mqnic_destroy_cq_ring(&interface->tx_cpl_ring[k]);
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for (k = 0; k < ARRAY_SIZE(interface->rx_ring); k++)
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if (interface->rx_ring[k])
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mqnic_destroy_rx_ring(&interface->rx_ring[k]);
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for (k = 0; k < ARRAY_SIZE(interface->rx_cpl_ring); k++)
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if (interface->rx_cpl_ring[k])
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mqnic_destroy_cq_ring(&interface->rx_cpl_ring[k]);
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// free ports
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for (k = 0; k < ARRAY_SIZE(interface->port); k++)
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if (interface->port[k])
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mqnic_destroy_port(&interface->port[k]);
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if (interface->rb_list)
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free_reg_block_list(interface->rb_list);
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*interface_ptr = NULL;
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kfree(interface);
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}
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u32 mqnic_interface_get_rss_mask(struct mqnic_if *interface)
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{
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return ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_RSS_MASK);
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}
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void mqnic_interface_set_rss_mask(struct mqnic_if *interface, u32 rss_mask)
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{
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iowrite32(rss_mask, interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_RSS_MASK);
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}
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u32 mqnic_interface_get_tx_mtu(struct mqnic_if *interface)
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{
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return ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_TX_MTU);
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}
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void mqnic_interface_set_tx_mtu(struct mqnic_if *interface, u32 mtu)
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{
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iowrite32(mtu, interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_TX_MTU);
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}
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u32 mqnic_interface_get_rx_mtu(struct mqnic_if *interface)
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{
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return ioread32(interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_RX_MTU);
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}
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void mqnic_interface_set_rx_mtu(struct mqnic_if *interface, u32 mtu)
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{
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iowrite32(mtu, interface->if_ctrl_rb->regs + MQNIC_RB_IF_CTRL_REG_RX_MTU);
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}
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