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FPGA
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corundum
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corundum
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fpga
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mqnic
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AU200
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fpga_100g
/
rtl
History
Alex Forencich
151ed7e179
Add extra reset registers
2021-01-31 11:10:03 -08:00
..
common
Add 100G mqnic design for Alveo U200
2020-09-22 01:01:07 -07:00
debounce_switch.v
Add 100G mqnic design for Alveo U200
2020-09-22 01:01:07 -07:00
fpga_core.v
Add pipeline registers, floorplanning constraints for AU200 100G design
2021-01-13 22:56:10 -08:00
fpga.v
Add extra reset registers
2021-01-31 11:10:03 -08:00
sync_signal.v
Add 100G mqnic design for Alveo U200
2020-09-22 01:01:07 -07:00
