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81 lines
2.0 KiB
Verilog
81 lines
2.0 KiB
Verilog
/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1 ns / 1 ps
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module test_arbiter;
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// parameters
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localparam PORTS = 32;
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localparam TYPE = "PRIORITY";
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localparam BLOCK = "REQUEST";
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg [PORTS-1:0] request = 0;
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reg [PORTS-1:0] acknowledge = 0;
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// Outputs
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wire [PORTS-1:0] grant;
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wire grant_valid;
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wire [$clog2(PORTS)-1:0] grant_encoded;
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initial begin
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// myhdl integration
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$from_myhdl(clk,
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rst,
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current_test,
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request,
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acknowledge);
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$to_myhdl(grant,
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grant_valid,
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grant_encoded);
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// dump file
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$dumpfile("test_arbiter.lxt");
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$dumpvars(0, test_arbiter);
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end
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arbiter #(
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.PORTS(PORTS),
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.TYPE(TYPE),
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.BLOCK(BLOCK)
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)
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UUT (
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.clk(clk),
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.rst(rst),
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.request(request),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded(grant_encoded)
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);
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endmodule
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