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32 lines
802 B
Markdown
32 lines
802 B
Markdown
# Verilog Ethernet RV901T Example Design
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## Introduction
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This example design targets the Linsn RV901T FPGA board.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
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will echo back any packets received. The design will also respond correctly
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to ARP requests.
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* FPGA: XC6SLX16T-2FT256
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* PHY: Broadcom B50612
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## How to build
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Run make to build. Ensure that the Xilinx ISE toolchain components are
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in PATH.
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## How to test
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Run make program to program the RV901T board with the Xilinx Impact software.
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Then run
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netcat -u 192.168.1.128 1234
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to open a UDP connection to port 1234. Any text entered into netcat will be
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echoed back after pressing enter.
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It is also possible to use hping to test the design by running
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hping 192.168.1.128 -2 -p 1234 -d 1024
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