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128 lines
5.2 KiB
ReStructuredText
128 lines
5.2 KiB
ReStructuredText
.. _rb_sched_ctrl_tdma:
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========================================
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TDMA scheduler controller register block
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========================================
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The TDMA scheduler controller register block has a header with type 0x0000C050, version 0x00000100, and indicates the location of the scheduler controller in the register space, as well as containing some control, status, and informational registers.
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.. table::
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======== ============= ====== ====== ====== ====== =============
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Address Field 31..24 23..16 15..8 7..0 Reset value
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======== ============= ====== ====== ====== ====== =============
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RBB+0x00 Type Vendor ID Type RO 0x0000C050
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-------- ------------- -------------- -------------- -------------
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RBB+0x04 Version Major Minor Patch Meta RO 0x00000100
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-------- ------------- ------ ------ ------ ------ -------------
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RBB+0x08 Next pointer Pointer to next register block RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x0C Offset Offset to scheduler RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x10 CH count Channel count RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x14 CH stride Channel stride RO -
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-------- ------------- ------------------------------ -------------
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RBB+0x18 Control Control RW 0x00000000
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-------- ------------- ------------------------------ -------------
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RBB+0x1C TS count TS count RW -
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======== ============= ============================== =============
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See :ref:`rb_overview` for definitions of the standard register block header fields.
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.. object:: Offset
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The offset field contains the offset to the start of the scheduler, relative to the start of the current region.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x0C Offset to scheduler RO -
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======== ============================== =============
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.. object:: Channel count
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The channel count field contains the number of channels.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x10 Channel count RO -
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======== ============================== =============
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.. object:: Channel stride
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The channel stride field contains the size of the region for each channel.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x14 Channel stride RO -
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======== ============================== =============
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.. object:: Control
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The control field contains scheduler-related control bits.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x18 Control RW 0x00000000
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======== ============================== =============
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.. object:: Timeslot count
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The timeslot count register contains the number of time slots supported.
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.. table::
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======== ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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======== ====== ====== ====== ====== =============
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RBB+0x1C Timeslot count RO -
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======== ============================== =============
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TDMA scheduler controller CSRs
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==============================
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Each scheduler control channel has several associated control registers, detailed in this table:
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.. table::
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========= ============== ====== ====== ====== ====== =============
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Address Field 31..24 23..16 15..8 7..0 Reset value
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========= ============== ====== ====== ====== ====== =============
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Base+0x00 Enable bits Enable bits RW -
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--------- -------------- ------------------------------ -------------
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Base+N Enable bits Enable bits RW -
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========= ============== ============================== =============
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.. object:: Enable bits
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The enable bits field contains per-timeslot channel enable bits.
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.. table::
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========= ====== ====== ====== ====== =============
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Address 31..24 23..16 15..8 7..0 Reset value
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========= ====== ====== ====== ====== =============
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Base+0x00 Enable bits RW 0x00000000
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========= ============================== =============
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.. table::
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=== =================
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Bit Function
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=== =================
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0 Timeslot 0 enable
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N Timeslot N enable
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=== =================
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