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https://github.com/corundum/corundum.git
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791 lines
20 KiB
Python
Executable File
791 lines
20 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2014-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import struct
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import axis_ep
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module = 'axis_stat_counter'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DATA_WIDTH = 64
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KEEP_WIDTH = (DATA_WIDTH/8)
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TAG_ENABLE = 1
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TAG_WIDTH = 16
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TICK_COUNT_ENABLE = 1
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TICK_COUNT_WIDTH = 32
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BYTE_COUNT_ENABLE = 1
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BYTE_COUNT_WIDTH = 32
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FRAME_COUNT_ENABLE = 1
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FRAME_COUNT_WIDTH = 32
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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monitor_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
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monitor_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
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monitor_axis_tvalid = Signal(bool(0))
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monitor_axis_tready = Signal(bool(0))
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monitor_axis_tlast = Signal(bool(0))
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monitor_axis_tuser = Signal(bool(0))
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m_axis_tready = Signal(bool(0))
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tag = Signal(intbv(16)[TAG_WIDTH:])
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trigger = Signal(bool(0))
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# Outputs
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m_axis_tdata = Signal(intbv(0)[8:])
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m_axis_tvalid = Signal(bool(0))
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m_axis_tlast = Signal(bool(0))
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m_axis_tuser = Signal(bool(0))
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busy = Signal(bool(0))
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# sources and sinks
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source_pause = Signal(bool(0))
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monitor_sink_pause = Signal(bool(0))
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource()
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source_logic = source.create_logic(
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clk,
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rst,
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tdata=monitor_axis_tdata,
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tkeep=monitor_axis_tkeep,
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tvalid=monitor_axis_tvalid,
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tready=monitor_axis_tready,
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tlast=monitor_axis_tlast,
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tuser=monitor_axis_tuser,
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pause=source_pause,
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name='source'
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)
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monitor_sink = axis_ep.AXIStreamSink()
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monitor_sink_logic = monitor_sink.create_logic(
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clk,
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rst,
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tdata=monitor_axis_tdata,
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tkeep=monitor_axis_tkeep,
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tvalid=monitor_axis_tvalid,
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tready=monitor_axis_tready,
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tlast=monitor_axis_tlast,
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tuser=monitor_axis_tuser,
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pause=monitor_sink_pause,
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name='monitor_sink'
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)
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sink = axis_ep.AXIStreamSink()
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sink_logic = sink.create_logic(
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clk,
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rst,
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tdata=m_axis_tdata,
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tvalid=m_axis_tvalid,
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tready=m_axis_tready,
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tlast=m_axis_tlast,
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tuser=m_axis_tuser,
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pause=sink_pause,
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name='sink'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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monitor_axis_tdata=monitor_axis_tdata,
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monitor_axis_tkeep=monitor_axis_tkeep,
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monitor_axis_tvalid=monitor_axis_tvalid,
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monitor_axis_tready=monitor_axis_tready,
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monitor_axis_tlast=monitor_axis_tlast,
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monitor_axis_tuser=monitor_axis_tuser,
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m_axis_tdata=m_axis_tdata,
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m_axis_tvalid=m_axis_tvalid,
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m_axis_tready=m_axis_tready,
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m_axis_tlast=m_axis_tlast,
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m_axis_tuser=m_axis_tuser,
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tag=tag,
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trigger=trigger,
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busy=busy
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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tag.next = 1
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yield clk.posedge
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print("test 1: test tick timer")
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current_test.next = 1
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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for i in range(100-1):
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[1] == 100*8
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yield delay(100)
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yield clk.posedge
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print("test 2: pause sink")
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current_test.next = 2
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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for i in range(100-1):
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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while trigger or m_axis_tvalid:
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sink_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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sink_pause.next = False
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[1] == 100*8
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yield delay(100)
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yield clk.posedge
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print("test 3: test packet")
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current_test.next = 3
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
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)
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source.send(test_frame)
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yield clk.posedge
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while monitor_axis_tvalid:
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[2] == len(test_frame.data)
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assert rx_frame_values[3] == 1
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yield delay(100)
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yield clk.posedge
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print("test 4: longer packet")
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current_test.next = 4
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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bytearray(range(256))
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)
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source.send(test_frame)
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yield clk.posedge
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while monitor_axis_tvalid:
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[2] == len(test_frame.data)
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assert rx_frame_values[3] == 1
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yield delay(100)
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yield clk.posedge
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print("test 5: test packet with pauses")
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current_test.next = 5
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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test_frame = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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bytearray(range(256))
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)
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source.send(test_frame)
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yield clk.posedge
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yield delay(64)
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yield clk.posedge
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source_pause.next = True
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yield delay(32)
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yield clk.posedge
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source_pause.next = False
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yield delay(64)
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yield clk.posedge
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monitor_sink_pause.next = True
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yield delay(32)
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yield clk.posedge
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monitor_sink_pause.next = False
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while monitor_axis_tvalid:
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[2] == len(test_frame.data)
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assert rx_frame_values[3] == 1
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yield delay(100)
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yield clk.posedge
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print("test 6: back-to-back packets")
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current_test.next = 6
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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test_frame1 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
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)
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test_frame2 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
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)
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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while monitor_axis_tvalid:
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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rx_frame = sink.recv()
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rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
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cycles = (stop_time - start_time) / 8
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print(rx_frame_values)
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assert rx_frame_values[0] == 1
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assert rx_frame_values[1] == cycles*8
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assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
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assert rx_frame_values[3] == 2
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yield delay(100)
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yield clk.posedge
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print("test 7: alternate pause source")
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current_test.next = 7
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yield clk.posedge
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start_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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test_frame1 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
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)
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test_frame2 = axis_ep.AXIStreamFrame(
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b'\xDA\xD1\xD2\xD3\xD4\xD5' +
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b'\x5A\x51\x52\x53\x54\x55' +
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b'\x80\x00' +
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b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
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)
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source.send(test_frame1)
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source.send(test_frame2)
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yield clk.posedge
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while monitor_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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source_pause.next = False
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yield clk.posedge
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source_pause.next = True
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yield clk.posedge
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source_pause.next = False
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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stop_time = now()
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trigger.next = 1
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yield clk.posedge
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trigger.next = 0
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yield clk.posedge
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while m_axis_tvalid:
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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# discard first trigger output
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rx_frame = sink.recv()
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# check second trigger output
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|
rx_frame = sink.recv()
|
|
|
|
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
|
|
cycles = (stop_time - start_time) / 8
|
|
print(rx_frame_values)
|
|
|
|
assert rx_frame_values[0] == 1
|
|
assert rx_frame_values[1] == cycles*8
|
|
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
|
|
assert rx_frame_values[3] == 2
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 8: alternate pause sink")
|
|
current_test.next = 8
|
|
|
|
yield clk.posedge
|
|
start_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
|
|
test_frame1 = axis_ep.AXIStreamFrame(
|
|
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
|
b'\x5A\x51\x52\x53\x54\x55' +
|
|
b'\x80\x00' +
|
|
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
|
|
)
|
|
test_frame2 = axis_ep.AXIStreamFrame(
|
|
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
|
b'\x5A\x51\x52\x53\x54\x55' +
|
|
b'\x80\x00' +
|
|
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10'
|
|
)
|
|
|
|
source.send(test_frame1)
|
|
source.send(test_frame2)
|
|
yield clk.posedge
|
|
|
|
while monitor_axis_tvalid:
|
|
monitor_sink_pause.next = True
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
monitor_sink_pause.next = False
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
|
|
yield clk.posedge
|
|
stop_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
|
|
# discard first trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
# check second trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
|
|
cycles = (stop_time - start_time) / 8
|
|
print(rx_frame_values)
|
|
|
|
assert rx_frame_values[0] == 1
|
|
assert rx_frame_values[1] == cycles*8
|
|
assert rx_frame_values[2] == len(test_frame1.data) + len(test_frame2.data)
|
|
assert rx_frame_values[3] == 2
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 9: various length packets")
|
|
current_test.next = 9
|
|
|
|
yield clk.posedge
|
|
start_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
|
|
lens = [32, 48, 96, 128, 256]
|
|
test_frame = []
|
|
|
|
for i in range(len(lens)):
|
|
test_frame.append(axis_ep.AXIStreamFrame(
|
|
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
|
b'\x5A\x51\x52\x53\x54\x55' +
|
|
b'\x80\x00' +
|
|
bytearray(range(lens[i])))
|
|
)
|
|
|
|
for f in test_frame:
|
|
source.send(f)
|
|
yield clk.posedge
|
|
|
|
while monitor_axis_tvalid:
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
|
|
yield clk.posedge
|
|
stop_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
|
|
# discard first trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
# check second trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
|
|
cycles = (stop_time - start_time) / 8
|
|
print(rx_frame_values)
|
|
|
|
assert rx_frame_values[0] == 1
|
|
assert rx_frame_values[1] == cycles*8
|
|
assert rx_frame_values[2] == sum(len(f.data) for f in test_frame)
|
|
assert rx_frame_values[3] == len(test_frame)
|
|
|
|
yield delay(100)
|
|
|
|
yield clk.posedge
|
|
print("test 10: various length packets with intermediate trigger")
|
|
current_test.next = 10
|
|
|
|
yield clk.posedge
|
|
start_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
|
|
lens = [32, 48, 96, 128, 256]
|
|
test_frame = []
|
|
|
|
for i in range(len(lens)):
|
|
test_frame.append(axis_ep.AXIStreamFrame(
|
|
b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
|
b'\x5A\x51\x52\x53\x54\x55' +
|
|
b'\x80\x00' +
|
|
bytearray(range(lens[i])))
|
|
)
|
|
|
|
for f in test_frame:
|
|
source.send(f)
|
|
yield clk.posedge
|
|
|
|
yield delay(200)
|
|
|
|
yield clk.posedge
|
|
trigger_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
yield clk.posedge
|
|
|
|
while monitor_axis_tvalid:
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
|
|
yield clk.posedge
|
|
stop_time = now()
|
|
trigger.next = 1
|
|
yield clk.posedge
|
|
trigger.next = 0
|
|
yield clk.posedge
|
|
|
|
while m_axis_tvalid:
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
yield clk.posedge
|
|
|
|
# discard first trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
# check second trigger output
|
|
rx_frame = sink.recv()
|
|
|
|
# check second trigger output
|
|
rx_frame2 = sink.recv()
|
|
|
|
rx_frame_values = struct.unpack(">HLLL", bytes(rx_frame.data))
|
|
cycles = (stop_time - start_time) / 8
|
|
cycles1 = (trigger_time - start_time) / 8
|
|
print(rx_frame_values)
|
|
|
|
rx_frame2_values = struct.unpack(">HLLL", bytes(rx_frame2.data))
|
|
cycles2 = (stop_time - trigger_time) / 8
|
|
print(rx_frame2_values)
|
|
|
|
assert rx_frame_values[0] == 1
|
|
assert rx_frame2_values[0] == 1
|
|
assert rx_frame_values[1] == cycles1*8
|
|
assert rx_frame2_values[1] == cycles2*8
|
|
assert rx_frame_values[1] + rx_frame2_values[1] == cycles*8
|
|
assert rx_frame_values[2] + rx_frame2_values[2] == sum(len(f.data) for f in test_frame)
|
|
assert rx_frame_values[3] + rx_frame2_values[3] == len(test_frame)
|
|
|
|
yield delay(100)
|
|
|
|
raise StopSimulation
|
|
|
|
return instances()
|
|
|
|
def test_bench():
|
|
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
|
sim = Simulation(bench())
|
|
sim.run()
|
|
|
|
if __name__ == '__main__':
|
|
print("Running test...")
|
|
test_bench()
|
|
|