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corundum/fpga/mqnic/VCU118/fpga_25g/rtl
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Alex Forencich bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-04-10 15:05:32 -07:00
..
common
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00
debounce_switch.v
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00
fpga_core.v
Add RX indirection table
2023-04-10 15:05:32 -07:00
fpga.v
Add RX indirection table
2023-04-10 15:05:32 -07:00
sync_signal.v
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00