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corundum/fpga/common/rtl
History
Alex Forencich 7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-04-21 13:15:45 -07:00
..
cmac_pad.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
cpl_op_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
cpl_queue_manager.v
fix partial initialisation of memory
2022-03-24 15:50:25 -07:00
cpl_write.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_fetch.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
desc_op_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
eth_xcvr_phy_10g_gty_quad_wrapper.v
Add common 10G PHY + GTH/GTY transceiver wrapper module
2022-03-02 17:28:40 -08:00
eth_xcvr_phy_10g_gty_wrapper.v
Rename cores to match transceiver type
2022-03-03 22:41:34 -08:00
event_mux.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
mqnic_core_axi.v
Add application ID
2022-04-21 13:15:45 -07:00
mqnic_core_pcie_s10.v
Add application ID
2022-04-21 13:15:45 -07:00
mqnic_core_pcie_us.v
Add application ID
2022-04-21 13:15:45 -07:00
mqnic_core_pcie.v
Add application ID
2022-04-21 13:15:45 -07:00
mqnic_core.v
Add application ID
2022-04-21 13:15:45 -07:00
mqnic_egress.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
mqnic_ingress.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
mqnic_interface_rx.v
Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter
2022-02-15 18:01:43 -08:00
mqnic_interface_tx.v
Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter
2022-02-15 18:01:43 -08:00
mqnic_interface.v
fpga: Add DMA immediate connections and parameters
2022-04-20 15:00:58 -07:00
mqnic_l2_egress.v
Add layer 2 ingress/egress modules
2022-02-13 23:09:41 -08:00
mqnic_l2_ingress.v
Add layer 2 ingress/egress modules
2022-02-13 23:09:41 -08:00
mqnic_port_map_mac_axis.v
fpga/common: Add port mapping modules
2022-04-12 21:16:17 -07:00
mqnic_port_map_phy_xgmii.v
fpga/common: Add port mapping modules
2022-04-12 21:16:17 -07:00
mqnic_ptp_clock.v
Pass through PTP pipelining settings
2022-03-28 00:50:29 -07:00
mqnic_ptp_perout.v
Register space reorganization
2021-12-29 22:31:46 -08:00
mqnic_ptp.v
Pass through PTP pipelining settings
2022-03-28 00:50:29 -07:00
mqnic_tx_scheduler_block_rr_tdma.v
Add SCHED_PER_IF parameter to split scheduler count from port count
2022-03-28 15:20:33 -07:00
mqnic_tx_scheduler_block_rr.v
Add SCHED_PER_IF parameter to split scheduler count from port count
2022-03-28 15:20:33 -07:00
queue_manager.v
fix partial initialisation of memory
2022-03-24 15:50:25 -07:00
rb_drp.v
Add DRP register block
2022-02-21 23:20:54 -08:00
rx_checksum.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
rx_engine.v
Add some more parameter checks
2022-02-14 00:41:28 -08:00
rx_fifo.v
Add missing parameter connection in rx_fifo
2022-01-26 09:44:35 -08:00
rx_hash.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_collect.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_counter.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_dma_if_pcie.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_dma_latency.v
Add attributes to RAMs for proper synthesis in Quartus
2021-11-06 16:14:22 -07:00
stats_pcie_if.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
stats_pcie_tlp.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tdma_ber_ch.v
Fix TDMA BER pipeline register
2022-03-17 13:28:41 -07:00
tdma_ber.v
Add pipeline registers to TDMA BER modules
2022-03-15 17:40:27 -07:00
tdma_scheduler.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_checksum.v
Remove debug code
2021-11-06 16:14:32 -07:00
tx_engine.v
Add some more parameter checks
2022-02-14 00:41:28 -08:00
tx_fifo.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
tx_req_mux.v
Initial implementation of shared interface datapath
2021-12-31 14:33:31 -08:00
tx_scheduler_ctrl_tdma.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00
tx_scheduler_rr.v
fix partial initialisation of memory
2022-03-24 15:50:25 -07:00