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397 lines
11 KiB
Verilog
397 lines
11 KiB
Verilog
/*
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Copyright 2021, The Regents of the University of California.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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The views and conclusions contained in the software and documentation are those
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of the authors and should not be interpreted as representing official policies,
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either expressed or implied, of The Regents of the University of California.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* NIC ingress processing
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*/
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module mqnic_ingress #
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(
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// Request tag field width
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parameter REQ_TAG_WIDTH = 8,
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// Receive queue index width
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parameter RX_QUEUE_INDEX_WIDTH = 8,
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// Enable RX RSS
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parameter RX_RSS_ENABLE = 1,
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// Enable RX hashing
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parameter RX_HASH_ENABLE = 1,
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// Enable RX checksum offload
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parameter RX_CHECKSUM_ENABLE = 1,
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// Width of AXI stream interfaces in bits
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parameter AXIS_DATA_WIDTH = 256,
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// AXI stream tkeep signal width (words per cycle)
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parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
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// AXI stream tid signal width
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parameter AXIS_ID_WIDTH = 8,
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// AXI stream tdest signal width
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parameter AXIS_DEST_WIDTH = 8,
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// AXI stream tuser signal width
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parameter AXIS_USER_WIDTH = 1,
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// Max receive packet size
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parameter MAX_RX_SIZE = 2048
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Receive data input
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*/
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
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/*
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* Receive data output
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*/
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
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/*
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* RX command output
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*/
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output wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue,
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output wire [REQ_TAG_WIDTH-1:0] rx_req_tag,
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output wire rx_req_valid,
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input wire rx_req_ready,
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/*
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* RX hash output
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*/
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output wire [31:0] rx_hash,
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output wire [3:0] rx_hash_type,
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output wire rx_hash_valid,
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input wire rx_hash_ready,
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/*
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* RX checksum output
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*/
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output wire [15:0] rx_csum,
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output wire rx_csum_valid,
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input wire rx_csum_ready,
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/*
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* Configuration
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*/
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input wire [31:0] rss_mask
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);
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generate
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wire [31:0] rx_hash_int;
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wire [3:0] rx_hash_type_int;
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wire rx_hash_valid_int;
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if (RX_HASH_ENABLE) begin
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rx_hash #(
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.DATA_WIDTH(AXIS_DATA_WIDTH)
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)
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rx_hash_inst (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa),
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.m_axis_hash(rx_hash_int),
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.m_axis_hash_type(rx_hash_type_int),
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.m_axis_hash_valid(rx_hash_valid_int)
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);
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axis_fifo #(
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.DEPTH(32),
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.DATA_WIDTH(32+4),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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rx_hash_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata({rx_hash_type_int, rx_hash_int}),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_hash_valid_int),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata({rx_hash_type, rx_hash}),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_hash_valid),
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.m_axis_tready(rx_hash_ready),
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.m_axis_tlast(),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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end else begin
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assign rx_hash = 32'd0;
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assign rx_hash_type = 4'd0;
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assign rx_hash_valid = 1'b0;
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end
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if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin
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axis_fifo #(
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.DEPTH(AXIS_KEEP_WIDTH*32),
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.DATA_WIDTH(AXIS_DATA_WIDTH),
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.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
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.KEEP_WIDTH(AXIS_KEEP_WIDTH),
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.LAST_ENABLE(1),
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.ID_ENABLE(1),
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.ID_WIDTH(AXIS_ID_WIDTH),
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.DEST_ENABLE(1),
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.DEST_WIDTH(AXIS_DEST_WIDTH),
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.USER_ENABLE(1),
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.USER_WIDTH(AXIS_USER_WIDTH),
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.FRAME_FIFO(0)
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)
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rx_hash_data_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.s_axis_tid(s_axis_tid),
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.s_axis_tdest(s_axis_tdest),
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.s_axis_tuser(s_axis_tuser),
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// AXI output
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tkeep(m_axis_tkeep),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tid(m_axis_tid),
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.m_axis_tdest(m_axis_tdest),
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.m_axis_tuser(m_axis_tuser),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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// Generate RX requests (RSS)
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assign rx_req_tag = 0;
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axis_fifo #(
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.DEPTH(32),
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.DATA_WIDTH(RX_QUEUE_INDEX_WIDTH),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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rx_req_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(rx_hash_int & rss_mask),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_hash_valid_int),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata(rx_req_queue),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_req_valid),
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.m_axis_tready(rx_req_ready),
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.m_axis_tlast(),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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end else begin
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assign m_axis_tdata = s_axis_tdata;
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assign m_axis_tkeep = s_axis_tkeep;
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assign m_axis_tvalid = s_axis_tvalid;
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assign s_axis_tready = m_axis_tready;
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assign m_axis_tlast = s_axis_tlast;
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assign m_axis_tid = s_axis_tid;
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assign m_axis_tdest = s_axis_tdest;
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assign m_axis_tuser = s_axis_tuser;
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// Generate RX requests (no RSS)
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reg rx_frame_reg = 1'b0;
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reg rx_req_valid_reg = 1'b0;
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assign rx_req_queue = 0;
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assign rx_req_tag = 0;
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assign rx_req_valid = s_axis_tvalid && !rx_frame_reg;
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always @(posedge clk) begin
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if (rx_req_ready) begin
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rx_req_valid_reg <= 1'b0;
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end
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if (s_axis_tready && s_axis_tvalid) begin
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if (!rx_frame_reg) begin
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rx_req_valid_reg <= 1'b1;
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end
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rx_frame_reg <= !s_axis_tlast;
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end
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if (rst) begin
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rx_frame_reg <= 1'b0;
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rx_req_valid_reg <= 1'b0;
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end
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end
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end
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if (RX_CHECKSUM_ENABLE) begin
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wire [15:0] rx_csum_int;
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wire rx_csum_valid_int;
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rx_checksum #(
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.DATA_WIDTH(AXIS_DATA_WIDTH)
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)
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rx_checksum_inst (
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.clk(clk),
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.rst(rst),
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tkeep(s_axis_tkeep),
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.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
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.s_axis_tlast(s_axis_tlast),
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.m_axis_csum(rx_csum_int),
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.m_axis_csum_valid(rx_csum_valid_int)
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);
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axis_fifo #(
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.DEPTH(32),
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.DATA_WIDTH(16),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(0),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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rx_csum_fifo (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(rx_csum_int),
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.s_axis_tkeep(0),
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.s_axis_tvalid(rx_csum_valid_int),
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.s_axis_tready(),
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.s_axis_tlast(0),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata(rx_csum),
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.m_axis_tkeep(),
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.m_axis_tvalid(rx_csum_valid),
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.m_axis_tready(rx_csum_ready),
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.m_axis_tlast(),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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end else begin
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assign rx_csum = 16'd0;
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assign rx_csum_valid = 1'b0;
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end
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endgenerate
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endmodule
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`resetall
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