mirror of
https://github.com/corundum/corundum.git
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207 lines
6.1 KiB
Python
Executable File
207 lines
6.1 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an AXI Stream crosspoint switch with the specified number of ports
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"""
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from __future__ import print_function
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import argparse
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import math
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if type(ports) is int:
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m = n = ports
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elif len(ports) == 1:
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m = n = ports[0]
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else:
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m, n = ports
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if name is None:
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name = "axis_crosspoint_64_{0}x{1}".format(m, n)
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if output is None:
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output = name + ".v"
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print("Opening file '{0}'...".format(output))
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output_file = open(output, 'w')
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print("Generating {0}x{1} port AXI Stream crosspoint {2}...".format(m, n, name))
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select_width = int(math.ceil(math.log(m, 2)))
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t = Template(u"""/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream {{m}}x{{n}} crosspoint (64 bit datapath)
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*/
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module {{name}} #
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(
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI Stream inputs
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*/
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{%- for p in range(m) %}
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input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep,
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input wire input_{{p}}_axis_tvalid,
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input wire input_{{p}}_axis_tlast,
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input wire input_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* AXI Stream outputs
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*/
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{%- for p in range(n) %}
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output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep,
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output wire output_{{p}}_axis_tvalid,
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output wire output_{{p}}_axis_tlast,
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output wire output_{{p}}_axis_tuser,
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{% endfor %}
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/*
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* Control
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*/
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{%- for p in range(n) %}
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input wire [{{w-1}}:0] output_{{p}}_select{% if not loop.last %},{% endif %}
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{%- endfor %}
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);
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{% for p in range(m) %}
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reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg input_{{p}}_axis_tvalid_reg = 1'b0;
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reg input_{{p}}_axis_tlast_reg = 1'b0;
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reg input_{{p}}_axis_tuser_reg = 1'b0;
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{% endfor %}
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{%- for p in range(n) %}
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reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = {DATA_WIDTH{1'b0}};
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reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
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reg output_{{p}}_axis_tvalid_reg = 1'b0;
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reg output_{{p}}_axis_tlast_reg = 1'b0;
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reg output_{{p}}_axis_tuser_reg = 1'b0;
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{% endfor %}
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{%- for p in range(n) %}
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reg [{{w-1}}:0] output_{{p}}_select_reg = {{w}}'d0;
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{%- endfor %}
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{% for p in range(n) %}
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assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg;
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assign output_{{p}}_axis_tkeep = output_{{p}}_axis_tkeep_reg;
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assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg;
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assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg;
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assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg;
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{% endfor %}
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always @(posedge clk) begin
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if (rst) begin
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{%- for p in range(n) %}
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output_{{p}}_select_reg <= {{w}}'d0;
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{%- endfor %}
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{% for p in range(m) %}
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input_{{p}}_axis_tvalid_reg <= 1'b0;
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{%- endfor %}
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{% for p in range(n) %}
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output_{{p}}_axis_tvalid_reg <= 1'b0;
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{%- endfor %}
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end else begin
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{%- for p in range(m) %}
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input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid;
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{%- endfor %}
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{% for p in range(n) %}
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output_{{p}}_select_reg <= output_{{p}}_select;
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{%- endfor %}
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{%- for p in range(n) %}
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case (output_{{p}}_select_reg)
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{%- for q in range(m) %}
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{{w}}'d{{q}}: output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg;
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{%- endfor %}
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endcase
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{%- endfor %}
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end
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{%- for p in range(m) %}
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input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata;
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input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep;
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input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast;
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input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser;
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{%- endfor %}
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{%- for p in range(n) %}
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case (output_{{p}}_select_reg)
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{%- for q in range(m) %}
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{{w}}'d{{q}}: begin
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output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg;
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output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg;
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output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg;
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output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg;
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end
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{%- endfor %}
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endcase
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{%- endfor %}
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end
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endmodule
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""")
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output_file.write(t.render(
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m=m,
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n=n,
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w=select_width,
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name=name
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))
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print("Done")
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if __name__ == "__main__":
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main()
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