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1d729817a6
To not overwhelm any logging daemon. Full TX queues can be quite common depending on a system's context and capabilities. Mostly all the details are not required anyway in such cases. To enable such debug messages and have their text turn up in dmesg and logging daemons, the mqnic module has to be compiled with CPP symbol DEBUG being (`make DEBUG=yes`) defined, or the kernel in use has to support "Dynamic Debug" [1]. In the latter case all such debug messages in module mqnic can be enabled with: echo 'module mqnic +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control To enable just this specific messages, based on its (partial) format: echo 'format "TX ring %d full" +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control [1] https://www.kernel.org/doc/html/latest/admin-guide/dynamic-debug-howto.html Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
524 lines
12 KiB
C
524 lines
12 KiB
C
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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#include <linux/version.h>
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#include "mqnic.h"
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struct mqnic_ring *mqnic_create_tx_ring(struct mqnic_if *interface)
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{
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struct mqnic_ring *ring;
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ring = kzalloc(sizeof(*ring), GFP_KERNEL);
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if (!ring)
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return ERR_PTR(-ENOMEM);
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ring->dev = interface->dev;
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ring->interface = interface;
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ring->index = -1;
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ring->enabled = 0;
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ring->hw_addr = NULL;
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ring->hw_ptr_mask = 0xffff;
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ring->hw_head_ptr = NULL;
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ring->hw_tail_ptr = NULL;
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ring->head_ptr = 0;
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ring->tail_ptr = 0;
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return ring;
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}
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void mqnic_destroy_tx_ring(struct mqnic_ring *ring)
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{
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mqnic_close_tx_ring(ring);
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kfree(ring);
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}
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int mqnic_open_tx_ring(struct mqnic_ring *ring, struct mqnic_priv *priv,
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struct mqnic_cq *cq, int size, int desc_block_size)
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{
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int ret = 0;
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if (ring->enabled || ring->hw_addr || ring->buf || !priv || !cq)
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return -EINVAL;
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ring->index = mqnic_res_alloc(ring->interface->txq_res);
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if (ring->index < 0)
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return -ENOMEM;
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ring->log_desc_block_size = desc_block_size < 2 ? 0 : ilog2(desc_block_size - 1) + 1;
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ring->desc_block_size = 1 << ring->log_desc_block_size;
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ring->size = roundup_pow_of_two(size);
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ring->full_size = ring->size >> 1;
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ring->size_mask = ring->size - 1;
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ring->stride = roundup_pow_of_two(MQNIC_DESC_SIZE * ring->desc_block_size);
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ring->tx_info = kvzalloc(sizeof(*ring->tx_info) * ring->size, GFP_KERNEL);
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if (!ring->tx_info) {
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ret = -ENOMEM;
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goto fail;
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}
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ring->buf_size = ring->size * ring->stride;
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ring->buf = dma_alloc_coherent(ring->dev, ring->buf_size, &ring->buf_dma_addr, GFP_KERNEL);
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if (!ring->buf) {
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ret = -ENOMEM;
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goto fail;
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}
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ring->priv = priv;
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ring->cq = cq;
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cq->src_ring = ring;
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cq->handler = mqnic_tx_irq;
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ring->hw_addr = mqnic_res_get_addr(ring->interface->txq_res, ring->index);
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ring->hw_head_ptr = ring->hw_addr + MQNIC_QUEUE_HEAD_PTR_REG;
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ring->hw_tail_ptr = ring->hw_addr + MQNIC_QUEUE_TAIL_PTR_REG;
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ring->head_ptr = 0;
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ring->tail_ptr = 0;
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// deactivate queue
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iowrite32(0, ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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// set base address
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iowrite32(ring->buf_dma_addr, ring->hw_addr + MQNIC_QUEUE_BASE_ADDR_REG + 0);
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iowrite32(ring->buf_dma_addr >> 32, ring->hw_addr + MQNIC_QUEUE_BASE_ADDR_REG + 4);
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// set CQN
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iowrite32(ring->cq->cqn, ring->hw_addr + MQNIC_QUEUE_CPL_QUEUE_INDEX_REG);
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// set pointers
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iowrite32(ring->head_ptr & ring->hw_ptr_mask, ring->hw_addr + MQNIC_QUEUE_HEAD_PTR_REG);
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iowrite32(ring->tail_ptr & ring->hw_ptr_mask, ring->hw_addr + MQNIC_QUEUE_TAIL_PTR_REG);
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// set size
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8),
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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return 0;
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fail:
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mqnic_close_tx_ring(ring);
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return ret;
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}
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void mqnic_close_tx_ring(struct mqnic_ring *ring)
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{
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mqnic_disable_tx_ring(ring);
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if (ring->cq) {
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ring->cq->src_ring = NULL;
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ring->cq->handler = NULL;
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}
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ring->priv = NULL;
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ring->cq = NULL;
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ring->hw_addr = NULL;
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ring->hw_head_ptr = NULL;
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ring->hw_tail_ptr = NULL;
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if (ring->buf) {
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mqnic_free_tx_buf(ring);
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dma_free_coherent(ring->dev, ring->buf_size, ring->buf, ring->buf_dma_addr);
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ring->buf = NULL;
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ring->buf_dma_addr = 0;
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}
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if (ring->tx_info) {
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kvfree(ring->tx_info);
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ring->tx_info = NULL;
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}
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mqnic_res_free(ring->interface->txq_res, ring->index);
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ring->index = -1;
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}
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int mqnic_enable_tx_ring(struct mqnic_ring *ring)
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{
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if (!ring->hw_addr)
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return -EINVAL;
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// enable queue
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8) | MQNIC_QUEUE_ACTIVE_MASK,
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->enabled = 1;
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return 0;
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}
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void mqnic_disable_tx_ring(struct mqnic_ring *ring)
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{
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// disable queue
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if (ring->hw_addr) {
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8),
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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}
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ring->enabled = 0;
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}
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bool mqnic_is_tx_ring_empty(const struct mqnic_ring *ring)
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{
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return ring->head_ptr == ring->tail_ptr;
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}
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bool mqnic_is_tx_ring_full(const struct mqnic_ring *ring)
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{
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return ring->head_ptr - ring->tail_ptr >= ring->full_size;
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}
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void mqnic_tx_read_tail_ptr(struct mqnic_ring *ring)
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{
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ring->tail_ptr += (ioread32(ring->hw_tail_ptr) - ring->tail_ptr) & ring->hw_ptr_mask;
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}
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void mqnic_tx_write_head_ptr(struct mqnic_ring *ring)
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{
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iowrite32(ring->head_ptr & ring->hw_ptr_mask, ring->hw_head_ptr);
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}
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void mqnic_free_tx_desc(struct mqnic_ring *ring, int index, int napi_budget)
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{
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struct mqnic_tx_info *tx_info = &ring->tx_info[index];
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struct sk_buff *skb = tx_info->skb;
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u32 i;
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prefetchw(&skb->users);
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dma_unmap_single(ring->dev, dma_unmap_addr(tx_info, dma_addr),
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dma_unmap_len(tx_info, len), DMA_TO_DEVICE);
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dma_unmap_addr_set(tx_info, dma_addr, 0);
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// unmap frags
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for (i = 0; i < tx_info->frag_count; i++)
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dma_unmap_page(ring->dev, tx_info->frags[i].dma_addr,
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tx_info->frags[i].len, DMA_TO_DEVICE);
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napi_consume_skb(skb, napi_budget);
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tx_info->skb = NULL;
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}
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int mqnic_free_tx_buf(struct mqnic_ring *ring)
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{
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u32 index;
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int cnt = 0;
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while (!mqnic_is_tx_ring_empty(ring)) {
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index = ring->tail_ptr & ring->size_mask;
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mqnic_free_tx_desc(ring, index, 0);
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ring->tail_ptr++;
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cnt++;
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}
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return cnt;
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}
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int mqnic_process_tx_cq(struct mqnic_cq *cq, int napi_budget)
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{
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struct mqnic_if *interface = cq->interface;
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struct mqnic_ring *tx_ring = cq->src_ring;
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struct mqnic_priv *priv = tx_ring->priv;
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struct mqnic_tx_info *tx_info;
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struct mqnic_cpl *cpl;
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struct skb_shared_hwtstamps hwts;
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u32 cq_index;
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u32 cq_tail_ptr;
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u32 ring_index;
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u32 ring_tail_ptr;
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u32 packets = 0;
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u32 bytes = 0;
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int done = 0;
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int budget = napi_budget;
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if (unlikely(!priv || !priv->port_up))
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return done;
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// prefetch for BQL
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netdev_txq_bql_complete_prefetchw(tx_ring->tx_queue);
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// process completion queue
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cq_tail_ptr = cq->tail_ptr;
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cq_index = cq_tail_ptr & cq->size_mask;
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while (done < budget) {
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cpl = (struct mqnic_cpl *)(cq->buf + cq_index * cq->stride);
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if (!!(cpl->phase & cpu_to_le32(0x80000000)) == !!(cq_tail_ptr & cq->size))
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break;
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dma_rmb();
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ring_index = le16_to_cpu(cpl->index) & tx_ring->size_mask;
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tx_info = &tx_ring->tx_info[ring_index];
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// TX hardware timestamp
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if (unlikely(tx_info->ts_requested)) {
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netdev_info(priv->ndev, "%s: TX TS requested", __func__);
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hwts.hwtstamp = mqnic_read_cpl_ts(interface->mdev, tx_ring, cpl);
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skb_tstamp_tx(tx_info->skb, &hwts);
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}
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// free TX descriptor
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mqnic_free_tx_desc(tx_ring, ring_index, napi_budget);
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packets++;
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bytes += le16_to_cpu(cpl->len);
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done++;
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cq_tail_ptr++;
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cq_index = cq_tail_ptr & cq->size_mask;
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}
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// update CQ tail
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cq->tail_ptr = cq_tail_ptr;
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mqnic_cq_write_tail_ptr(cq);
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// process ring
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ring_tail_ptr = READ_ONCE(tx_ring->tail_ptr);
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ring_index = ring_tail_ptr & tx_ring->size_mask;
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while (ring_tail_ptr != tx_ring->head_ptr) {
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tx_info = &tx_ring->tx_info[ring_index];
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if (tx_info->skb)
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break;
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ring_tail_ptr++;
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ring_index = ring_tail_ptr & tx_ring->size_mask;
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}
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// update ring tail
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WRITE_ONCE(tx_ring->tail_ptr, ring_tail_ptr);
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// BQL
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//netdev_tx_completed_queue(tx_ring->tx_queue, packets, bytes);
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// wake queue if it is stopped
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if (netif_tx_queue_stopped(tx_ring->tx_queue) && !mqnic_is_tx_ring_full(tx_ring))
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netif_tx_wake_queue(tx_ring->tx_queue);
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return done;
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}
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void mqnic_tx_irq(struct mqnic_cq *cq)
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{
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napi_schedule_irqoff(&cq->napi);
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}
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int mqnic_poll_tx_cq(struct napi_struct *napi, int budget)
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{
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struct mqnic_cq *cq = container_of(napi, struct mqnic_cq, napi);
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int done;
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done = mqnic_process_tx_cq(cq, budget);
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if (done == budget)
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return done;
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napi_complete(napi);
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mqnic_arm_cq(cq);
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return done;
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}
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static bool mqnic_map_skb(struct mqnic_ring *ring, struct mqnic_tx_info *tx_info,
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struct mqnic_desc *tx_desc, struct sk_buff *skb)
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{
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struct skb_shared_info *shinfo = skb_shinfo(skb);
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const skb_frag_t *frag;
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u32 i;
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u32 len;
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dma_addr_t dma_addr;
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// update tx_info
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tx_info->skb = skb;
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tx_info->frag_count = 0;
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for (i = 0; i < shinfo->nr_frags; i++) {
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frag = &shinfo->frags[i];
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len = skb_frag_size(frag);
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dma_addr = skb_frag_dma_map(ring->dev, frag, 0, len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(ring->dev, dma_addr)))
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// mapping failed
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goto map_error;
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// write descriptor
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tx_desc[i + 1].len = cpu_to_le32(len);
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tx_desc[i + 1].addr = cpu_to_le64(dma_addr);
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// update tx_info
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tx_info->frag_count = i + 1;
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tx_info->frags[i].len = len;
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tx_info->frags[i].dma_addr = dma_addr;
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}
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for (i = tx_info->frag_count; i < ring->desc_block_size - 1; i++) {
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tx_desc[i + 1].len = 0;
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tx_desc[i + 1].addr = 0;
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}
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// map skb
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len = skb_headlen(skb);
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dma_addr = dma_map_single(ring->dev, skb->data, len, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(ring->dev, dma_addr)))
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// mapping failed
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goto map_error;
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// write descriptor
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tx_desc[0].len = cpu_to_le32(len);
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tx_desc[0].addr = cpu_to_le64(dma_addr);
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// update tx_info
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dma_unmap_addr_set(tx_info, dma_addr, dma_addr);
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dma_unmap_len_set(tx_info, len, len);
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return true;
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map_error:
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dev_err(ring->dev, "%s: DMA mapping failed", __func__);
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// unmap frags
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for (i = 0; i < tx_info->frag_count; i++)
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dma_unmap_page(ring->dev, tx_info->frags[i].dma_addr,
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tx_info->frags[i].len, DMA_TO_DEVICE);
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// update tx_info
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tx_info->skb = NULL;
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tx_info->frag_count = 0;
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return false;
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}
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netdev_tx_t mqnic_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct skb_shared_info *shinfo = skb_shinfo(skb);
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struct mqnic_priv *priv = netdev_priv(ndev);
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struct mqnic_ring *ring;
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struct mqnic_tx_info *tx_info;
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struct mqnic_desc *tx_desc;
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int ring_index;
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u32 index;
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bool stop_queue;
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u32 tail_ptr;
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if (unlikely(!priv->port_up))
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goto tx_drop;
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ring_index = skb_get_queue_mapping(skb);
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rcu_read_lock();
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ring = radix_tree_lookup(&priv->txq_table, ring_index);
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rcu_read_unlock();
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if (unlikely(!ring))
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// unknown TX queue
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goto tx_drop;
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tail_ptr = READ_ONCE(ring->tail_ptr);
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// prefetch for BQL
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netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
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index = ring->head_ptr & ring->size_mask;
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tx_desc = (struct mqnic_desc *)(ring->buf + index * ring->stride);
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tx_info = &ring->tx_info[index];
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// TX hardware timestamp
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tx_info->ts_requested = 0;
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if (unlikely(priv->if_features & MQNIC_IF_FEATURE_PTP_TS && shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
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netdev_info(ndev, "%s: TX TS requested", __func__);
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shinfo->tx_flags |= SKBTX_IN_PROGRESS;
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tx_info->ts_requested = 1;
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}
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// TX hardware checksum
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if (skb->ip_summed == CHECKSUM_PARTIAL) {
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unsigned int csum_start = skb_checksum_start_offset(skb);
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unsigned int csum_offset = skb->csum_offset;
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if (csum_start > 255 || csum_offset > 127) {
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netdev_info(ndev, "%s: Hardware checksum fallback start %d offset %d",
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__func__, csum_start, csum_offset);
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// offset out of range, fall back on software checksum
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if (skb_checksum_help(skb)) {
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// software checksumming failed
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goto tx_drop_count;
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}
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tx_desc->tx_csum_cmd = 0;
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} else {
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tx_desc->tx_csum_cmd = cpu_to_le16(0x8000 | (csum_offset << 8) | (csum_start));
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}
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} else {
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tx_desc->tx_csum_cmd = 0;
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}
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if (shinfo->nr_frags > ring->desc_block_size - 1 || (skb->data_len && skb->data_len < 32)) {
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// too many frags or very short data portion; linearize
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if (skb_linearize(skb))
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goto tx_drop_count;
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}
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// map skb
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if (!mqnic_map_skb(ring, tx_info, tx_desc, skb))
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// map failed
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goto tx_drop_count;
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// count packet
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ring->packets++;
|
|
ring->bytes += skb->len;
|
|
|
|
// enqueue
|
|
ring->head_ptr++;
|
|
|
|
skb_tx_timestamp(skb);
|
|
|
|
stop_queue = mqnic_is_tx_ring_full(ring);
|
|
if (unlikely(stop_queue)) {
|
|
netdev_dbg(ndev, "%s: TX ring %d full on port %d",
|
|
__func__, ring_index, priv->index);
|
|
netif_tx_stop_queue(ring->tx_queue);
|
|
}
|
|
|
|
// BQL
|
|
//netdev_tx_sent_queue(ring->tx_queue, tx_info->len);
|
|
//__netdev_tx_sent_queue(ring->tx_queue, tx_info->len, skb->xmit_more);
|
|
|
|
// enqueue on NIC
|
|
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0)
|
|
if (unlikely(!netdev_xmit_more() || stop_queue)) {
|
|
#else
|
|
if (unlikely(!skb->xmit_more || stop_queue)) {
|
|
#endif
|
|
dma_wmb();
|
|
mqnic_tx_write_head_ptr(ring);
|
|
}
|
|
|
|
// check if queue restarted
|
|
if (unlikely(stop_queue)) {
|
|
smp_rmb();
|
|
|
|
tail_ptr = READ_ONCE(ring->tail_ptr);
|
|
|
|
if (unlikely(!mqnic_is_tx_ring_full(ring)))
|
|
netif_tx_wake_queue(ring->tx_queue);
|
|
}
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
tx_drop_count:
|
|
ring->dropped_packets++;
|
|
tx_drop:
|
|
dev_kfree_skb_any(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|