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871 lines
33 KiB
ReStructuredText
871 lines
33 KiB
ReStructuredText
.. _mod_mqnic_core:
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==============
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``mqnic_core``
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==============
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``mqnic_core`` is the core integration-level module for mqnic for all host interfaces. Contains the interfaces, asynchronous FIFOs, PTP subsystem, statistics collection subsystem, and application block.
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For maximum flexibility, this module does not contain the actual host-facing DMA engine, so a wrapper is required to provide the DMA engine with the proper host-facing interface. The available wrappers are:
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* :ref:`mod_mqnic_core_pcie` for PCI express
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* :ref:`mod_mqnic_core_axi` for AXI
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``mqnic_core`` integrates the following modules:
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* ``stats_counter``: statistics aggregation
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* :ref:`mod_mqnic_ptp`: PTP subsystem
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* :ref:`mod_mqnic_interface`: NIC interface
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* :ref:`mod_mqnic_app_block`: Application block
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Parameters
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==========
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.. object:: FPGA_ID
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FPGA JTAG ID, default is ``32'hDEADBEEF``. Reported in :ref:`rb_fw_id`.
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.. object:: FW_ID
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Firmware ID, default is ``32'h00000000``. Reported in :ref:`rb_fw_id`.
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.. object:: FW_VER
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Firmware version, default is ``32'h00_00_01_00``. Reported in :ref:`rb_fw_id`.
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.. object:: BOARD_ID
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Board ID, default is ``16'h1234_0000``. Reported in :ref:`rb_fw_id`.
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.. object:: BOARD_VER
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Board version, default is ``32'h01_00_00_00``. Reported in :ref:`rb_fw_id`.
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.. object:: BUILD_DATE
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Build date as a 32-bit unsigned Unix timestamp, default is ``32'd602976000``. Reported in :ref:`rb_fw_id`.
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.. object:: GIT_HASH
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32 bits of the git commit hash, default is ``32'hdce357bf``. Reported in :ref:`rb_fw_id`.
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.. object:: RELEASE_INFO
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Additional release info, default is ``32'h00000000``. Reported in :ref:`rb_fw_id`.
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.. object:: IF_COUNT
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Interface count, default ``1``.
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.. object:: PORTS_PER_IF
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Ports per interface, default ``1``.
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.. object:: PORT_COUNT
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Total port count, must be set to ``IF_COUNT*PORTS_PER_IF``.
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.. object:: PTP_TS_WIDTH
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PTP timestamp width, must be ``96``.
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.. object:: PTP_TAG_WIDTH
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PTP tag signal width, default ``16``.
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.. object:: PTP_PERIOD_NS_WIDTH
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PTP period ns field width, default ``4``.
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.. object:: PTP_OFFSET_NS_WIDTH
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PTP offset ns field width, default ``32``.
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.. object:: PTP_FNS_WIDTH
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PTP fractional ns field width, default ``32``.
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.. object:: PTP_PERIOD_NS
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PTP nominal period, ns portion, default ``4'd4``.
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.. object:: PTP_PERIOD_FNS
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PTP nominal period, fractional ns portion, default ``32'd0``.
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.. object:: PTP_USE_SAMPLE_CLOCK
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Use external PTP sample clock, used to synchronize the PTP clock across clock domains, default ``0``.
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.. object:: PTP_SEPARATE_RX_CLOCK
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Use ``rx_ptp_clk`` instead of ``rx_clk`` for providing current PTP time if set, default ``0``.
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.. object:: PTP_PEROUT_ENABLE
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Enable PTP period output module, default ``0``.
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.. object:: PTP_PEROUT_COUNT
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Number of PTP period output channels, default ``1``.
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.. object:: EVENT_QUEUE_OP_TABLE_SIZE
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Event queue manager operation table size, default ``32``.
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.. object:: TX_QUEUE_OP_TABLE_SIZE
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Transmit queue manager operation table size, default ``32``.
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.. object:: RX_QUEUE_OP_TABLE_SIZE
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Receive queue manager operation table size, default ``32``.
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.. object:: TX_CPL_QUEUE_OP_TABLE_SIZE
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Transmit completion queue operation table size, default ``TX_QUEUE_OP_TABLE_SIZE``.
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.. object:: RX_CPL_QUEUE_OP_TABLE_SIZE
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Receive completion queue operation table size, default ``RX_QUEUE_OP_TABLE_SIZE``.
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.. object:: TX_QUEUE_INDEX_WIDTH
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Transmit queue index width, default ``13``. Sets the number of transmit queues on each interfaces as ``2**TX_QUEUE_INDEX_WIDTH``.
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.. object:: RX_QUEUE_INDEX_WIDTH
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Receive queue index width, default ``8``. Sets the number of receive queues on each interfaces as ``2**RX_QUEUE_INDEX_WIDTH``.
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.. object:: TX_CPL_QUEUE_INDEX_WIDTH
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Transmit completion queue index width, default ``TX_QUEUE_INDEX_WIDTH``. Sets the number of transmit completion queues on each interfaces as ``2**TX_CPL_QUEUE_INDEX_WIDTH``.
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.. object:: RX_CPL_QUEUE_INDEX_WIDTH
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Receive completion queue index width, default ``RX_QUEUE_INDEX_WIDTH``. Sets the number of receive completion queues on each interfaces as ``2**RX_CPL_QUEUE_INDEX_WIDTH``.
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.. object:: EVENT_QUEUE_PIPELINE
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Event queue manager pipeline length, default ``3``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: TX_QUEUE_PIPELINE
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Transmit queue manager pipeline stages, default ``3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0)``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: RX_QUEUE_PIPELINE
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Receive queue manager pipeline stages, default ``3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0)``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: TX_CPL_QUEUE_PIPELINE
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Transmit completion queue manager pipeline stages, default ``TX_QUEUE_PIPELINE``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: RX_CPL_QUEUE_PIPELINE
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Receive completion queue maanger pipeline stages, default ``RX_QUEUE_PIPELINE``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: TX_DESC_TABLE_SIZE
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Transmit engine descriptor table size, default ``32``.
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.. object:: RX_DESC_TABLE_SIZE
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Receive engine descriptor table size, default ``32``.
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.. object:: TX_SCHEDULER_OP_TABLE_SIZE
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Transmit scheduler operation table size, default ``TX_DESC_TABLE_SIZE``.
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.. object:: TX_SCHEDULER_PIPELINE
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Transmit scheduler pipeline stages, default ``TX_QUEUE_PIPELINE``. Tune for best usage of block RAM cascade registers for specified queue count.
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.. object:: TDMA_INDEX_WIDTH
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TDMA index width, default ``6``. Sets the number of TDMA timeslots as ``2**TDMA_INDEX_WIDTH``.
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.. object:: PTP_TS_ENABLE
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Enable PTP timestamping, default ``1``.
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.. object:: TX_PTP_TS_FIFO_DEPTH
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Depth of TX PTP timestamp FIFO, default ``32``.
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.. object:: RX_PTP_TS_FIFO_DEPTH
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Depth of RX PTP timestamp FIFO, default ``32``.
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.. object:: TX_CHECKSUM_ENABLE
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Enable TCP/UDP checksum offloading on transmit path, default ``1``.
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.. object:: RX_RSS_ENABLE
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Enable receive side scaling, default ``1``. Requires ``RX_HASH_ENABLE`` to be set.
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.. object:: RX_HASH_ENABLE
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Enable Toeplitz flow hashing for RX traffic, default ``1``.
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.. object:: RX_CHECKSUM_ENABLE
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Enable TCP/UDP checksum offloading on receive path, default ``1``
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.. object:: TX_FIFO_DEPTH
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Transmit FIFO depth in bytes, per output port, per traffic class, default ``32768``.
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.. object:: RX_FIFO_DEPTH
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Receive FIFO depth in bytes, per output port, default ``32768``.
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.. object:: MAX_TX_SIZE
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Maximum packet size on transmit path, default ``9214``.
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.. object:: MAX_RX_SIZE
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Maximum packet size on receive path, default ``9214``.
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.. object:: TX_RAM_SIZE
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Transmit scratchpad RAM size per interface, default ``32768``.
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.. object:: RX_RAM_SIZE
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Receive scratchpad RAM size per interface, default ``32768``.
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.. object:: APP_ENABLE
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Enable application section, default ``0``.
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.. object:: APP_CTRL_ENABLE
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Enable application section control connection to core NIC registers, default ``1``.
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.. object:: APP_DMA_ENABLE
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Enable application section connection to DMA subsystem, default ``1``.
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.. object:: APP_AXIS_DIRECT_ENABLE
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Enable lowest-latency asynchronous streaming connection to application section, default ``1``
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.. object:: APP_AXIS_SYNC_ENABLE
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Enable low-latency synchronous streaming connection to application section, default ``1``
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.. object:: APP_AXIS_IF_ENABLE
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Enable interface-level streaming connection to application section, default ``1``
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.. object:: APP_STAT_ENABLE
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Enable application section connection to statistics collection subsystem, default ``1``
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.. object:: APP_GPIO_IN_WIDTH
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Application section GPIO input signal width, default ``32``
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.. object:: APP_GPIO_OUT_WIDTH
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Application section GPIO output signal width, default ``32``
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.. object:: DMA_ADDR_WIDTH
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DMA interface address signal width, default ``64``.
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.. object:: DMA_LEN_WIDTH
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DMA interface length signal width, default ``16``.
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.. object:: DMA_TAG_WIDTH
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DMA interface tag signal width, default ``16``.
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.. object:: IF_RAM_SEL_WIDTH
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Width of interface-level select signal, default ``1``.
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.. object:: RAM_SEL_WIDTH
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Width of select signal per segment in DMA RAM interface, default ``$clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1``.
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.. object:: RAM_ADDR_WIDTH
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Width of address signal for DMA RAM interface, default ``$clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE)``.
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.. object:: RAM_SEG_COUNT
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Number of segments in DMA RAM interface, default ``2``. Must be a power of 2, must be at least 2.
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.. object:: RAM_SEG_DATA_WIDTH
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Width of data signal per segment in DMA RAM interface, default ``256*2/RAM_SEG_COUNT``.
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.. object:: RAM_SEG_BE_WIDTH
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Width of byte enable signal per segment in DMA RAM interface, must be set to ``RAM_SEG_DATA_WIDTH/8``.
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.. object:: RAM_SEG_ADDR_WIDTH
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Width of address signal per segment in DMA RAM interface, default ``RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH)``.
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.. object:: RAM_PIPELINE
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Number of output pipeline stages in segmented DMA RAMs, default ``2``. Tune for best usage of block RAM cascade registers.
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.. object:: MSI_COUNT
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Number of interrupt channels, default ``32``.
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.. object:: AXIL_CTRL_DATA_WIDTH
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AXI lite control data signal width, must be set to ``32``.
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.. object:: AXIL_CTRL_ADDR_WIDTH
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AXI lite control address signal width, default ``16``.
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.. object:: AXIL_CTRL_STRB_WIDTH
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AXI lite control byte enable signal width, must be set to ``AXIL_CTRL_DATA_WIDTH/8``.
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.. object:: AXIL_IF_CTRL_ADDR_WIDTH
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AXI lite interface control address signal width, default ``AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT)``
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.. object:: AXIL_CSR_ADDR_WIDTH
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AXI lite interface CSR address signal width, default ``AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8)``
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.. object:: AXIL_CSR_PASSTHROUGH_ENABLE
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Enable NIC control register space passthrough, default ``0``.
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.. object:: RB_NEXT_PTR
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Next pointer of last register block in the NIC-level CSR space, default ``0``.
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.. object:: AXIL_APP_CTRL_DATA_WIDTH
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AXI lite application control data signal width, default ``AXIL_CTRL_DATA_WIDTH``. Can be 32 or 64.
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.. object:: AXIL_APP_CTRL_ADDR_WIDTH
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AXI lite application control address signal width, default ``16``.
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.. object:: AXIL_APP_CTRL_STRB_WIDTH
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AXI lite application control byte enable signal width, must be set to ``AXIL_APP_CTRL_DATA_WIDTH/8``.
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.. object:: AXIS_DATA_WIDTH
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Streaming interface ``tdata`` signal width, default ``512``.
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.. object:: AXIS_KEEP_WIDTH
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Streaming interface ``tkeep`` signal width, must be set to ``AXIS_DATA_WIDTH/8``.
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.. object:: AXIS_SYNC_DATA_WIDTH
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Synchronous streaming interface ``tdata`` signal width, default ``AXIS_DATA_WIDTH``.
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.. object:: AXIS_IF_DATA_WIDTH
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Interface streaming interface ``tdata`` signal width, default ``AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF)``.
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.. object:: AXIS_TX_USER_WIDTH
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Transmit streaming interface ``tuser`` signal width, default ``(PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1``.
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.. object:: AXIS_RX_USER_WIDTH
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Receive streaming interface ``tuser`` signal width, default ``(PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1``.
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.. object:: AXIS_RX_USE_READY
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Use ``tready`` signal on RX interfaces, default ``0``. If set, logic will exert backpressure with ``tready`` instead of dropping packets when RX FIFOs are full.
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.. object:: AXIS_TX_PIPELINE
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Number of stages in transmit path pipeline FIFO, default ``0``. Useful for SLR crossings.
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.. object:: AXIS_TX_FIFO_PIPELINE
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Number of output pipeline stages in transmit FIFO, default ``2``. Tune for best usage of block RAM cascade registers.
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.. object:: AXIS_TX_TS_PIPELINE
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Number of stages in transmit path PTP timestamp pipeline FIFO, default ``0``. Useful for SLR crossings.
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.. object:: AXIS_RX_PIPELINE
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Number of stages in receive path pipeline FIFO, default ``0``. Useful for SLR crossings.
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.. object:: AXIS_RX_FIFO_PIPELINE
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Number of output pipeline stages in receive FIFO, default ``2``. Tune for best usage of block RAM cascade registers.
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.. object:: STAT_ENABLE
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Enable statistics collection subsystem, default ``1``.
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.. object:: STAT_INC_WIDTH
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Statistics increment signal width, default ``24``.
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.. object:: STAT_ID_WIDTH
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Statistics ID signal width, default ``12``. Sets the number of statistics counters as ``2**STAT_ID_WIDTH``.
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Ports
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=====
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.. object:: clk
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Logic clock. Most interfaces are synchronous to this clock.
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.. table::
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====== === ===== ==================
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Signal Dir Width Description
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====== === ===== ==================
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clk in 1 Logic clock
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====== === ===== ==================
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.. object:: rst
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Logic reset, active high
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.. table::
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====== === ===== ==================
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Signal Dir Width Description
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====== === ===== ==================
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rst in 1 Logic reset, active high
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====== === ===== ==================
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.. object:: s_axil_ctrl
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AXI-Lite slave interface (control). This interface provides access to the main NIC control register space.
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.. table::
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=================== === ==================== ===================
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Signal Dir Width Description
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=================== === ==================== ===================
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s_axil_ctrl_awaddr in AXIL_CTRL_ADDR_WIDTH Write address
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s_axil_ctrl_awprot in 3 Write protect
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s_axil_ctrl_awvalid in 1 Write address valid
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s_axil_ctrl_awready out 1 Write address ready
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s_axil_ctrl_wdata in AXIL_CTRL_DATA_WIDTH Write data
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s_axil_ctrl_wstrb in AXIL_CTRL_STRB_WIDTH Write data strobe
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s_axil_ctrl_wvalid in 1 Write data valid
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s_axil_ctrl_wready out 1 Write data ready
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s_axil_ctrl_bresp out 2 Write response status
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s_axil_ctrl_bvalid out 1 Write response valid
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s_axil_ctrl_bready in 1 Write response ready
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s_axil_ctrl_araddr in AXIL_CTRL_ADDR_WIDTH Read address
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s_axil_ctrl_arprot in 3 Read protect
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s_axil_ctrl_arvalid in 1 Read address valid
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s_axil_ctrl_arready out 1 Read address ready
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s_axil_ctrl_rdata out AXIL_CTRL_DATA_WIDTH Read response data
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s_axil_ctrl_rresp out 2 Read response status
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s_axil_ctrl_rvalid out 1 Read response valid
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s_axil_ctrl_rready in 1 Read response ready
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=================== === ==================== ===================
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.. object:: s_axil_app_ctrl
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AXI-Lite slave interface (application control). This interface is directly passed through to the application section.
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.. table::
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======================= === ======================== ===================
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Signal Dir Width Description
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======================= === ======================== ===================
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s_axil_app_ctrl_awaddr in AXIL_APP_CTRL_ADDR_WIDTH Write address
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s_axil_app_ctrl_awprot in 3 Write protect
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s_axil_app_ctrl_awvalid in 1 Write address valid
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s_axil_app_ctrl_awready out 1 Write address ready
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s_axil_app_ctrl_wdata in AXIL_APP_CTRL_DATA_WIDTH Write data
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s_axil_app_ctrl_wstrb in AXIL_APP_CTRL_STRB_WIDTH Write data strobe
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s_axil_app_ctrl_wvalid in 1 Write data valid
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s_axil_app_ctrl_wready out 1 Write data ready
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s_axil_app_ctrl_bresp out 2 Write response status
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s_axil_app_ctrl_bvalid out 1 Write response valid
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s_axil_app_ctrl_bready in 1 Write response ready
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s_axil_app_ctrl_araddr in AXIL_APP_CTRL_ADDR_WIDTH Read address
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s_axil_app_ctrl_arprot in 3 Read protect
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s_axil_app_ctrl_arvalid in 1 Read address valid
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s_axil_app_ctrl_arready out 1 Read address ready
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s_axil_app_ctrl_rdata out AXIL_APP_CTRL_DATA_WIDTH Read response data
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s_axil_app_ctrl_rresp out 2 Read response status
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s_axil_app_ctrl_rvalid out 1 Read response valid
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s_axil_app_ctrl_rready in 1 Read response ready
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======================= === ======================== ===================
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.. object:: m_axil_csr
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AXI-Lite master interface (passthrough for NIC control and status). This interface can be used to implement additional components in the main NIC control register space.
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.. table::
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================== === ==================== ===================
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Signal Dir Width Description
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================== === ==================== ===================
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m_axil_csr_awaddr in AXIL_CSR_ADDR_WIDTH Write address
|
|
m_axil_csr_awprot in 3 Write protect
|
|
m_axil_csr_awvalid in 1 Write address valid
|
|
m_axil_csr_awready out 1 Write address ready
|
|
m_axil_csr_wdata in AXIL_CTRL_DATA_WIDTH Write data
|
|
m_axil_csr_wstrb in AXIL_CTRL_STRB_WIDTH Write data strobe
|
|
m_axil_csr_wvalid in 1 Write data valid
|
|
m_axil_csr_wready out 1 Write data ready
|
|
m_axil_csr_bresp out 2 Write response status
|
|
m_axil_csr_bvalid out 1 Write response valid
|
|
m_axil_csr_bready in 1 Write response ready
|
|
m_axil_csr_araddr in AXIL_CTRL_ADDR_WIDTH Read address
|
|
m_axil_csr_arprot in 3 Read protect
|
|
m_axil_csr_arvalid in 1 Read address valid
|
|
m_axil_csr_arready out 1 Read address ready
|
|
m_axil_csr_rdata out AXIL_CTRL_DATA_WIDTH Read response data
|
|
m_axil_csr_rresp out 2 Read response status
|
|
m_axil_csr_rvalid out 1 Read response valid
|
|
m_axil_csr_rready in 1 Read response ready
|
|
================== === ==================== ===================
|
|
|
|
.. object:: ctrl_reg
|
|
|
|
Control register interface. This interface can be used to implement additional control registers and register blocks in the main NIC control register space.
|
|
|
|
.. table::
|
|
|
|
================= === ==================== ===================
|
|
Signal Dir Width Description
|
|
================= === ==================== ===================
|
|
ctrl_reg_wr_addr out AXIL_CSR_ADDR_WIDTH Write address
|
|
ctrl_reg_wr_data out AXIL_CTRL_DATA_WIDTH Write data
|
|
ctrl_reg_wr_strb out AXIL_CTRL_STRB_WIDTH Write strobe
|
|
ctrl_reg_wr_en out 1 Write enable
|
|
ctrl_reg_wr_wait in 1 Write wait
|
|
ctrl_reg_wr_ack in 1 Write acknowledge
|
|
ctrl_reg_rd_addr out AXIL_CSR_ADDR_WIDTH Read address
|
|
ctrl_reg_rd_en out 1 Read enable
|
|
ctrl_reg_rd_data in AXIL_CTRL_DATA_WIDTH Read data
|
|
ctrl_reg_rd_wait in 1 Read wait
|
|
ctrl_reg_rd_ack in 1 Read acknowledge
|
|
================= === ==================== ===================
|
|
|
|
.. object:: m_axis_dma_read_desc
|
|
|
|
DMA read descriptor output
|
|
|
|
.. table::
|
|
|
|
============================= === ============== ===================
|
|
Signal Dir Width Description
|
|
============================= === ============== ===================
|
|
m_axis_dma_read_desc_dma_addr out DMA_ADDR_WIDTH DMA address
|
|
m_axis_dma_read_desc_ram_sel out RAM_SEL_WIDTH RAM select
|
|
m_axis_dma_read_desc_ram_addr out RAM_ADDR_WIDTH RAM address
|
|
m_axis_dma_read_desc_len out DMA_LEN_WIDTH Transfer length
|
|
m_axis_dma_read_desc_tag out DMA_TAG_WIDTH Transfer tag
|
|
m_axis_dma_read_desc_valid out 1 Request valid
|
|
m_axis_dma_read_desc_ready in 1 Request ready
|
|
============================= === ============== ===================
|
|
|
|
.. object:: s_axis_dma_read_desc_status
|
|
|
|
DMA read descriptor status input
|
|
|
|
.. table::
|
|
|
|
================================= === ============= ===================
|
|
Signal Dir Width Description
|
|
================================= === ============= ===================
|
|
s_axis_dma_read_desc_status_tag in DMA_TAG_WIDTH Status tag
|
|
s_axis_dma_read_desc_status_error in 4 Status error code
|
|
s_axis_dma_read_desc_status_valid in 1 Status valid
|
|
================================= === ============= ===================
|
|
|
|
.. object:: m_axis_dma_write_desc
|
|
|
|
DMA write descriptor output
|
|
|
|
.. table::
|
|
|
|
============================== === ============== ===================
|
|
Signal Dir Width Description
|
|
============================== === ============== ===================
|
|
m_axis_dma_write_desc_dma_addr out DMA_ADDR_WIDTH DMA address
|
|
m_axis_dma_write_desc_ram_sel out RAM_SEL_WIDTH RAM select
|
|
m_axis_dma_write_desc_ram_addr out RAM_ADDR_WIDTH RAM address
|
|
m_axis_dma_write_desc_len out DMA_LEN_WIDTH Transfer length
|
|
m_axis_dma_write_desc_tag out DMA_TAG_WIDTH Transfer tag
|
|
m_axis_dma_write_desc_valid out 1 Request valid
|
|
m_axis_dma_write_desc_ready in 1 Request ready
|
|
============================== === ============== ===================
|
|
|
|
.. object:: s_axis_dma_write_desc_status
|
|
|
|
DMA write descriptor status input
|
|
|
|
.. table::
|
|
|
|
================================== === ============= ===================
|
|
Signal Dir Width Description
|
|
================================== === ============= ===================
|
|
s_axis_dma_write_desc_status_tag in DMA_TAG_WIDTH Status tag
|
|
s_axis_dma_write_desc_status_error in 4 Status error code
|
|
s_axis_dma_write_desc_status_valid in 1 Status valid
|
|
================================== === ============= ===================
|
|
|
|
.. object:: dma_ram
|
|
|
|
DMA RAM interface
|
|
|
|
.. table::
|
|
|
|
===================== === ================================ ===================
|
|
Signal Dir Width Description
|
|
===================== === ================================ ===================
|
|
dma_ram_wr_cmd_sel in RAM_SEG_COUNT*RAM_SEL_WIDTH Write command select
|
|
dma_ram_wr_cmd_be in RAM_SEG_COUNT*RAM_SEG_BE_WIDTH Write command byte enable
|
|
dma_ram_wr_cmd_addr in RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH Write command address
|
|
dma_ram_wr_cmd_data in RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH Write command data
|
|
dma_ram_wr_cmd_valid in RAM_SEG_COUNT Write command valid
|
|
dma_ram_wr_cmd_ready out RAM_SEG_COUNT Write command ready
|
|
dma_ram_wr_done out RAM_SEG_COUNT Write done
|
|
dma_ram_rd_cmd_sel in RAM_SEG_COUNT*RAM_SEL_WIDTH Read command select
|
|
dma_ram_rd_cmd_addr in RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH Read command address
|
|
dma_ram_rd_cmd_valid in RAM_SEG_COUNT Read command valid
|
|
dma_ram_rd_cmd_ready out RAM_SEG_COUNT Read command ready
|
|
dma_ram_rd_resp_data out RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH Read response data
|
|
dma_ram_rd_resp_valid out RAM_SEG_COUNT Read response valid
|
|
dma_ram_rd_resp_ready in RAM_SEG_COUNT Read response ready
|
|
===================== === ================================ ===================
|
|
|
|
.. object:: msi_irq
|
|
|
|
MSI request outputs
|
|
|
|
.. table::
|
|
|
|
======= === ========= ===================
|
|
Signal Dir Width Description
|
|
======= === ========= ===================
|
|
msi_irq out MSI_COUNT Interrupt request
|
|
======= === ========= ===================
|
|
|
|
.. object:: ptp
|
|
|
|
PTP clock connections.
|
|
|
|
.. table::
|
|
|
|
================= === ================ ===================
|
|
Signal Dir Width Description
|
|
================= === ================ ===================
|
|
ptp_sample_clk in 1 PTP sample clock
|
|
ptp_pps out 1 PTP pulse-per-second
|
|
ptp_ts_96 out PTP_TS_WIDTH current PTP time
|
|
ptp_ts_step out 1 PTP clock step
|
|
ptp_perout_locked out PTP_PEROUT_COUNT PTP period output locked
|
|
ptp_perout_error out PTP_PEROUT_COUNT PTP period output error
|
|
ptp_perout_pulse out PTP_PEROUT_COUNT PTP period output pulse
|
|
================= === ================ ===================
|
|
|
|
.. object:: tx_clk
|
|
|
|
Transmit clocks, one per port
|
|
|
|
.. table::
|
|
|
|
====== === ========== ==================
|
|
Signal Dir Width Description
|
|
====== === ========== ==================
|
|
tx_clk in PORT_COUNT Transmit clock
|
|
====== === ========== ==================
|
|
|
|
.. object:: tx_rst
|
|
|
|
Transmit resets, one per port
|
|
|
|
.. table::
|
|
|
|
====== === ========== ==================
|
|
Signal Dir Width Description
|
|
====== === ========== ==================
|
|
tx_rst in PORT_COUNT Transmit reset
|
|
====== === ========== ==================
|
|
|
|
.. object:: tx_ptp_ts
|
|
|
|
Reference PTP time for transmit timestamping synchronous to each transmit clock, one per port.
|
|
|
|
.. table::
|
|
|
|
============== === ======================= ==================
|
|
Signal Dir Width Description
|
|
============== === ======================= ==================
|
|
tx_ptp_ts_96 out PORT_COUNT*PTP_TS_WIDTH current PTP time
|
|
tx_ptp_ts_step out PORT_COUNT PTP clock step
|
|
============== === ======================= ==================
|
|
|
|
.. object:: m_axis_tx
|
|
|
|
Streaming transmit data towards network, one AXI stream interface per port.
|
|
|
|
.. table::
|
|
|
|
================ === ============================= ==================
|
|
Signal Dir Width Description
|
|
================ === ============================= ==================
|
|
m_axis_tx_tdata out PORT_COUNT*AXIS_DATA_WIDTH Streaming data
|
|
m_axis_tx_tkeep out PORT_COUNT*AXIS_KEEP_WIDTH Byte enable
|
|
m_axis_tx_tvalid out PORT_COUNT Data valid
|
|
m_axis_tx_tready in PORT_COUNT Ready for data
|
|
m_axis_tx_tlast out PORT_COUNT End of frame
|
|
m_axis_tx_tuser out PORT_COUNT*AXIS_TX_USER_WIDTH Sideband data
|
|
================ === ============================= ==================
|
|
|
|
``s_axis_tx_tuser`` bits, per port
|
|
|
|
.. table::
|
|
|
|
=============== ========= ============= =============
|
|
Bit Name Width Description
|
|
=============== ========= ============= =============
|
|
0 bad_frame 1 Invalid frame
|
|
PTP_TAG_WIDTH:1 ptp_tag PTP_TAG_WIDTH PTP tag
|
|
=============== ========= ============= =============
|
|
|
|
.. object:: s_axis_tx_ptp_ts
|
|
|
|
Transmit PTP timestamp, one AXI stream interface per port.
|
|
|
|
.. table::
|
|
|
|
====================== === ======================== ===================
|
|
Signal Dir Width Description
|
|
====================== === ======================== ===================
|
|
s_axis_tx_ptp_ts in PORT_COUNT*PTP_TS_WIDTH PTP timestamp
|
|
s_axis_tx_ptp_ts_tag in PORT_COUNT*PTP_TAG_WIDTH PTP timestamp tag
|
|
s_axis_tx_ptp_ts_valid in PORT_COUNT PTP timestamp valid
|
|
s_axis_tx_ptp_ts_ready out PORT_COUNT PTP timestamp ready
|
|
====================== === ======================== ===================
|
|
|
|
.. object:: rx_clk
|
|
|
|
Receive clocks, one per port
|
|
|
|
.. table::
|
|
|
|
====== === ========== ==================
|
|
Signal Dir Width Description
|
|
====== === ========== ==================
|
|
rx_clk in PORT_COUNT Receive clock
|
|
====== === ========== ==================
|
|
|
|
.. object:: rx_rst
|
|
|
|
Receive resets, one per port
|
|
|
|
.. table::
|
|
|
|
====== === ========== ==================
|
|
Signal Dir Width Description
|
|
====== === ========== ==================
|
|
rx_rst in PORT_COUNT Receive reset
|
|
====== === ========== ==================
|
|
|
|
.. object:: rx_ptp_ts
|
|
|
|
Reference PTP time for receive timestamping synchronous to each receive clock, one per port. Synchronous to ``rx_ptp_clk`` if ``PTP_SEPARATE_RX_CLOCK`` is set.
|
|
|
|
.. table::
|
|
|
|
============== === ======================= ==================
|
|
Signal Dir Width Description
|
|
============== === ======================= ==================
|
|
rx_ptp_clk in PORT_COUNT clock for PTP time
|
|
rx_ptp_rst in PORT_COUNT reset for PTP time
|
|
rx_ptp_ts_96 out PORT_COUNT*PTP_TS_WIDTH current PTP time
|
|
rx_ptp_ts_step out PORT_COUNT PTP clock step
|
|
============== === ======================= ==================
|
|
|
|
.. object:: s_axis_rx
|
|
|
|
Streaming receive data from network, one AXI stream interface per port.
|
|
|
|
.. table::
|
|
|
|
================ === ============================= ==================
|
|
Signal Dir Width Description
|
|
================ === ============================= ==================
|
|
s_axis_rx_tdata in PORT_COUNT*AXIS_DATA_WIDTH Streaming data
|
|
s_axis_rx_tkeep in PORT_COUNT*AXIS_KEEP_WIDTH Byte enable
|
|
s_axis_rx_tvalid in PORT_COUNT Data valid
|
|
s_axis_rx_tready out PORT_COUNT Ready for data
|
|
s_axis_rx_tlast in PORT_COUNT End of frame
|
|
s_axis_rx_tuser in PORT_COUNT*AXIS_TX_USER_WIDTH Sideband data
|
|
================ === ============================= ==================
|
|
|
|
``s_axis_rx_tuser`` bits, per port
|
|
|
|
.. table::
|
|
|
|
============== ========= ============ =============
|
|
Bit Name Width Description
|
|
============== ========= ============ =============
|
|
0 bad_frame 1 Invalid frame
|
|
PTP_TS_WIDTH:1 ptp_ts PTP_TS_WIDTH PTP timestamp
|
|
============== ========= ============ =============
|
|
|
|
.. object:: s_axis_stat
|
|
|
|
Statistics increment input
|
|
|
|
.. table::
|
|
|
|
================== === ============== ===================
|
|
Signal Dir Width Description
|
|
================== === ============== ===================
|
|
s_axis_stat_tdata in STAT_INC_WIDTH Statistic increment
|
|
s_axis_stat_tid in STAT_ID_WIDTH Statistic ID
|
|
s_axis_stat_tvalid in 1 Statistic valid
|
|
s_axis_stat_tready out 1 Statistic ready
|
|
================== === ============== ===================
|
|
|
|
.. object:: app_gpio
|
|
|
|
Application section GPIO
|
|
|
|
.. table::
|
|
|
|
============ === ================== ===================
|
|
Signal Dir Width Description
|
|
============ === ================== ===================
|
|
app_gpio_in in APP_GPIO_IN_WIDTH GPIO inputs
|
|
app_gpio_out out APP_GPIO_OUT_WIDTH GPIO outputs
|
|
============ === ================== ===================
|
|
|
|
.. object:: app_jtag
|
|
|
|
Application section JTAG scan chain
|
|
|
|
.. table::
|
|
|
|
============ === ===== ===================
|
|
Signal Dir Width Description
|
|
============ === ===== ===================
|
|
app_jtag_tdi in 1 JTAG TDI
|
|
app_jtag_tdo out 1 JTAG TDO
|
|
app_jtag_tms in 1 JTAG TMS
|
|
app_jtag_tck in 1 JTAG TCK
|
|
============ === ===== ===================
|