mirror of
https://github.com/corundum/corundum.git
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556 lines
13 KiB
Verilog
556 lines
13 KiB
Verilog
/*
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Copyright (c) 2020-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Clock: 125MHz LVDS
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* Reset: Push button, active low
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*/
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input wire clk_125mhz_p,
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input wire clk_125mhz_n,
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input wire reset,
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/*
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* GPIO
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*/
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input wire btnu,
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input wire btnl,
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input wire btnd,
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input wire btnr,
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input wire btnc,
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input wire [7:0] sw,
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output wire [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire uart_rxd,
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output wire uart_txd,
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input wire uart_rts,
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output wire uart_cts,
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/*
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* Ethernet: SFP+
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*/
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input wire sfp0_rx_p,
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input wire sfp0_rx_n,
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output wire sfp0_tx_p,
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output wire sfp0_tx_n,
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input wire sfp1_rx_p,
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input wire sfp1_rx_n,
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output wire sfp1_tx_p,
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output wire sfp1_tx_n,
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input wire sfp2_rx_p,
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input wire sfp2_rx_n,
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output wire sfp2_tx_p,
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output wire sfp2_tx_n,
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input wire sfp3_rx_p,
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input wire sfp3_rx_n,
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output wire sfp3_tx_p,
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output wire sfp3_tx_n,
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input wire sfp_mgt_refclk_0_p,
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input wire sfp_mgt_refclk_0_n,
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output wire sfp0_tx_disable_b,
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output wire sfp1_tx_disable_b,
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output wire sfp2_tx_disable_b,
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output wire sfp3_tx_disable_b
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);
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// Clock and reset
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wire clk_125mhz_ibufg;
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wire clk_125mhz_bufg;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS #(
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.DIFF_TERM("FALSE"),
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.IBUF_LOW_PWR("FALSE")
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)
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clk_125mhz_ibufg_inst (
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.O (clk_125mhz_ibufg),
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.I (clk_125mhz_p),
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.IB (clk_125mhz_n)
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);
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BUFG
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clk_125mhz_bufg_in_inst (
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.I(clk_125mhz_ibufg),
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.O(clk_125mhz_bufg)
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);
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// MMCM instance
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// 125 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
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// Divide by 8 to get output frequency of 125 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(8),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(1),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(8.0),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_125mhz_bufg),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [7:0] sw_int;
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debounce_switch #(
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.WIDTH(9),
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.N(8),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_rts_int;
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sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_156mhz_int),
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.in({uart_rxd, uart_rts}),
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.out({uart_rxd_int, uart_rts_int})
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);
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// XGMII 10G PHY
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assign sfp0_tx_disable_b = 1'b1;
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assign sfp1_tx_disable_b = 1'b1;
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assign sfp2_tx_disable_b = 1'b1;
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assign sfp3_tx_disable_b = 1'b1;
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wire sfp0_tx_clk_int;
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wire sfp0_tx_rst_int;
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wire [63:0] sfp0_txd_int;
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wire [7:0] sfp0_txc_int;
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wire sfp0_rx_clk_int;
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wire sfp0_rx_rst_int;
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wire [63:0] sfp0_rxd_int;
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wire [7:0] sfp0_rxc_int;
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wire sfp1_tx_clk_int;
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wire sfp1_tx_rst_int;
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wire [63:0] sfp1_txd_int;
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wire [7:0] sfp1_txc_int;
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wire sfp1_rx_clk_int;
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wire sfp1_rx_rst_int;
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wire [63:0] sfp1_rxd_int;
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wire [7:0] sfp1_rxc_int;
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wire sfp2_tx_clk_int;
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wire sfp2_tx_rst_int;
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wire [63:0] sfp2_txd_int;
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wire [7:0] sfp2_txc_int;
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wire sfp2_rx_clk_int;
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wire sfp2_rx_rst_int;
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wire [63:0] sfp2_rxd_int;
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wire [7:0] sfp2_rxc_int;
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wire sfp3_tx_clk_int;
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wire sfp3_tx_rst_int;
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wire [63:0] sfp3_txd_int;
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wire [7:0] sfp3_txc_int;
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wire sfp3_rx_clk_int;
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wire sfp3_rx_rst_int;
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wire [63:0] sfp3_rxd_int;
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wire [7:0] sfp3_rxc_int;
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assign clk_156mhz_int = sfp0_tx_clk_int;
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assign rst_156mhz_int = sfp0_tx_rst_int;
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wire sfp0_rx_block_lock;
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wire sfp1_rx_block_lock;
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wire sfp2_rx_block_lock;
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wire sfp3_rx_block_lock;
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wire sfp_mgt_refclk_0;
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IBUFDS_GTE4 ibufds_gte4_sfp_mgt_refclk_0_inst (
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.I (sfp_mgt_refclk_0_p),
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.IB (sfp_mgt_refclk_0_n),
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.CEB (1'b0),
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.O (sfp_mgt_refclk_0),
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.ODIV2 ()
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);
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wire sfp_qpll0lock;
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wire sfp_qpll0outclk;
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wire sfp_qpll0outrefclk;
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1)
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)
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sfp0_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(sfp_mgt_refclk_0),
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.xcvr_qpll0lock_out(sfp_qpll0lock),
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.xcvr_qpll0outclk_out(sfp_qpll0outclk),
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.xcvr_qpll0outrefclk_out(sfp_qpll0outrefclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(sfp0_tx_p),
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.xcvr_txn(sfp0_tx_n),
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.xcvr_rxp(sfp0_rx_p),
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.xcvr_rxn(sfp0_rx_n),
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// PHY connections
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.phy_tx_clk(sfp0_tx_clk_int),
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.phy_tx_rst(sfp0_tx_rst_int),
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.phy_xgmii_txd(sfp0_txd_int),
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.phy_xgmii_txc(sfp0_txc_int),
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.phy_rx_clk(sfp0_rx_clk_int),
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.phy_rx_rst(sfp0_rx_rst_int),
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.phy_xgmii_rxd(sfp0_rxd_int),
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.phy_xgmii_rxc(sfp0_rxc_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(sfp0_rx_block_lock),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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sfp1_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(sfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(sfp_qpll0outclk),
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.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(sfp1_tx_p),
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.xcvr_txn(sfp1_tx_n),
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.xcvr_rxp(sfp1_rx_p),
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.xcvr_rxn(sfp1_rx_n),
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// PHY connections
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.phy_tx_clk(sfp1_tx_clk_int),
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.phy_tx_rst(sfp1_tx_rst_int),
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.phy_xgmii_txd(sfp1_txd_int),
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.phy_xgmii_txc(sfp1_txc_int),
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.phy_rx_clk(sfp1_rx_clk_int),
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.phy_rx_rst(sfp1_rx_rst_int),
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.phy_xgmii_rxd(sfp1_rxd_int),
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.phy_xgmii_rxc(sfp1_rxc_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(sfp1_rx_block_lock),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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sfp2_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(sfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(sfp_qpll0outclk),
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.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(sfp2_tx_p),
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.xcvr_txn(sfp2_tx_n),
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.xcvr_rxp(sfp2_rx_p),
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.xcvr_rxn(sfp2_rx_n),
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// PHY connections
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.phy_tx_clk(sfp2_tx_clk_int),
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.phy_tx_rst(sfp2_tx_rst_int),
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.phy_xgmii_txd(sfp2_txd_int),
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.phy_xgmii_txc(sfp2_txc_int),
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.phy_rx_clk(sfp2_rx_clk_int),
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.phy_rx_rst(sfp2_rx_rst_int),
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.phy_xgmii_rxd(sfp2_rxd_int),
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.phy_xgmii_rxc(sfp2_rxc_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
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.phy_rx_bad_block(),
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(sfp2_rx_block_lock),
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.phy_rx_high_ber(),
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.phy_tx_prbs31_enable(),
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.phy_rx_prbs31_enable()
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);
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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sfp3_phy_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0outclk_out(),
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.xcvr_qpll0outrefclk_out(),
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// PLL in
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.xcvr_qpll0lock_in(sfp_qpll0lock),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(sfp_qpll0outclk),
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.xcvr_qpll0refclk_in(sfp_qpll0outrefclk),
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// Serial data
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.xcvr_txp(sfp3_tx_p),
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.xcvr_txn(sfp3_tx_n),
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.xcvr_rxp(sfp3_rx_p),
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.xcvr_rxn(sfp3_rx_n),
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// PHY connections
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.phy_tx_clk(sfp3_tx_clk_int),
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.phy_tx_rst(sfp3_tx_rst_int),
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.phy_xgmii_txd(sfp3_txd_int),
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.phy_xgmii_txc(sfp3_txc_int),
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.phy_rx_clk(sfp3_rx_clk_int),
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.phy_rx_rst(sfp3_rx_rst_int),
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.phy_xgmii_rxd(sfp3_rxd_int),
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.phy_xgmii_rxc(sfp3_rxc_int),
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.phy_tx_bad_block(),
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.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(sfp3_rx_block_lock),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.btnu(btnu_int),
|
|
.btnl(btnl_int),
|
|
.btnd(btnd_int),
|
|
.btnr(btnr_int),
|
|
.btnc(btnc_int),
|
|
.sw(sw_int),
|
|
.led(led),
|
|
/*
|
|
* UART: 115200 bps, 8N1
|
|
*/
|
|
.uart_rxd(uart_rxd_int),
|
|
.uart_txd(uart_txd),
|
|
.uart_rts(uart_rts_int),
|
|
.uart_cts(uart_cts),
|
|
/*
|
|
* Ethernet: SFP+
|
|
*/
|
|
.sfp0_tx_clk(sfp0_tx_clk_int),
|
|
.sfp0_tx_rst(sfp0_tx_rst_int),
|
|
.sfp0_txd(sfp0_txd_int),
|
|
.sfp0_txc(sfp0_txc_int),
|
|
.sfp0_rx_clk(sfp0_rx_clk_int),
|
|
.sfp0_rx_rst(sfp0_rx_rst_int),
|
|
.sfp0_rxd(sfp0_rxd_int),
|
|
.sfp0_rxc(sfp0_rxc_int),
|
|
.sfp1_tx_clk(sfp1_tx_clk_int),
|
|
.sfp1_tx_rst(sfp1_tx_rst_int),
|
|
.sfp1_txd(sfp1_txd_int),
|
|
.sfp1_txc(sfp1_txc_int),
|
|
.sfp1_rx_clk(sfp1_rx_clk_int),
|
|
.sfp1_rx_rst(sfp1_rx_rst_int),
|
|
.sfp1_rxd(sfp1_rxd_int),
|
|
.sfp1_rxc(sfp1_rxc_int),
|
|
.sfp2_tx_clk(sfp2_tx_clk_int),
|
|
.sfp2_tx_rst(sfp2_tx_rst_int),
|
|
.sfp2_txd(sfp2_txd_int),
|
|
.sfp2_txc(sfp2_txc_int),
|
|
.sfp2_rx_clk(sfp2_rx_clk_int),
|
|
.sfp2_rx_rst(sfp2_rx_rst_int),
|
|
.sfp2_rxd(sfp2_rxd_int),
|
|
.sfp2_rxc(sfp2_rxc_int),
|
|
.sfp3_tx_clk(sfp3_tx_clk_int),
|
|
.sfp3_tx_rst(sfp3_tx_rst_int),
|
|
.sfp3_txd(sfp3_txd_int),
|
|
.sfp3_txc(sfp3_txc_int),
|
|
.sfp3_rx_clk(sfp3_rx_clk_int),
|
|
.sfp3_rx_rst(sfp3_rx_rst_int),
|
|
.sfp3_rxd(sfp3_rxd_int),
|
|
.sfp3_rxc(sfp3_rxc_int)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|