mirror of
https://github.com/corundum/corundum.git
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920 lines
31 KiB
Python
920 lines
31 KiB
Python
"""
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Copyright (c) 2020-2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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from typing import NamedTuple
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import cocotb
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from cocotb.queue import Queue
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from cocotb.triggers import Event, RisingEdge
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from cocotb_bus.bus import Bus
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from cocotbext.axi.memory import Memory
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from cocotbext.axi import Region
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# master write helper objects
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class WriteCmd(NamedTuple):
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address: int
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data: bytes
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event: Event
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class SegWriteData:
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def __int__(self):
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self.addr = 0
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self.data = 0
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self.be = 0
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class WriteRespCmd(NamedTuple):
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address: int
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length: int
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segments: int
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first_seg: int
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event: Event
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class WriteResp(NamedTuple):
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address: int
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length: int
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# master read helper objects
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class ReadCmd(NamedTuple):
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address: int
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length: int
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event: Event
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class SegReadCmd:
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def __int__(self):
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self.addr = 0
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class ReadRespCmd(NamedTuple):
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address: int
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length: int
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segments: int
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first_seg: int
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event: Event
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class ReadResp(NamedTuple):
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address: int
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data: bytes
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def __bytes__(self):
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return self.data
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class BaseBus(Bus):
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_signals = ["data"]
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_optional_signals = []
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def __init__(self, entity=None, prefix=None, **kwargs):
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super().__init__(entity, prefix, self._signals, optional_signals=self._optional_signals, **kwargs)
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@classmethod
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def from_entity(cls, entity, **kwargs):
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return cls(entity, **kwargs)
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@classmethod
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def from_prefix(cls, entity, prefix, **kwargs):
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return cls(entity, prefix, **kwargs)
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class PsdpRamWriteBus(BaseBus):
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_signals = ["wr_cmd_be", "wr_cmd_addr", "wr_cmd_data", "wr_cmd_valid", "wr_cmd_ready", "wr_done"]
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class PsdpRamReadBus(BaseBus):
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_signals = ["rd_cmd_addr", "rd_cmd_valid", "rd_cmd_ready", "rd_resp_data", "rd_resp_valid", "rd_resp_ready"]
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class PsdpRamBus:
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def __init__(self, write=None, read=None, **kwargs):
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self.write = write
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self.read = read
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@classmethod
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def from_entity(cls, entity, **kwargs):
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write = PsdpRamWriteBus.from_entity(entity, **kwargs)
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read = PsdpRamReadBus.from_entity(entity, **kwargs)
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return cls(write, read)
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@classmethod
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def from_prefix(cls, entity, prefix, **kwargs):
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write = PsdpRamWriteBus.from_prefix(entity, prefix, **kwargs)
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read = PsdpRamReadBus.from_prefix(entity, prefix, **kwargs)
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return cls(write, read)
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@classmethod
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def from_channels(cls, wr, rd):
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write = PsdpRamWriteBus.from_channels(wr)
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read = PsdpRamReadBus.from_channels(rd)
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return cls(write, read)
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class PsdpRamMasterWrite(Region):
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def __init__(self, bus, clock, reset=None, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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if bus._name:
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
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else:
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}")
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self.log.info("Parallel Simple Dual Port RAM master model (write)")
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.pause = False
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self._pause_generator = None
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self._pause_cr = None
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self.in_flight_operations = 0
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self._idle = Event()
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self._idle.set()
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self.width = len(self.bus.wr_cmd_data)
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self.byte_size = 8
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self.byte_lanes = len(self.bus.wr_cmd_be)
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self.seg_count = len(self.bus.wr_cmd_valid)
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self.seg_data_width = self.width // self.seg_count
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self.seg_byte_lanes = self.seg_data_width // self.byte_size
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self.seg_addr_width = len(self.bus.wr_cmd_addr) // self.seg_count
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self.seg_be_width = self.seg_data_width // self.byte_size
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self.seg_data_mask = 2**self.seg_data_width-1
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self.seg_addr_mask = 2**self.seg_addr_width-1
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self.seg_be_mask = 2**self.seg_be_width-1
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self.address_width = self.seg_addr_width + (self.seg_byte_lanes*self.seg_count-1).bit_length()
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self.write_command_queue = Queue()
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self.write_command_queue.queue_occupancy_limit = 2
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self.current_write_command = None
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self.seg_write_queue = [Queue() for x in range(self.seg_count)]
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self.seg_write_resp_queue = [Queue() for x in range(self.seg_count)]
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self.int_write_resp_command_queue = Queue()
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self.current_write_resp_command = None
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super().__init__(2**self.address_width, **kwargs)
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self.log.info("Parallel Simple Dual Port RAM master model configuration:")
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" Segment count: %d", self.seg_count)
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self.log.info(" Segment addr width: %d bits", self.seg_addr_width)
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self.log.info(" Segment data width: %d bits (%d bytes)", self.seg_data_width, self.seg_byte_lanes)
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self.log.info(" Total data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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assert self.seg_be_width*self.seg_count == len(self.bus.wr_cmd_be)
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self.bus.wr_cmd_valid.setimmediatevalue(0)
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cocotb.start_soon(self._process_write())
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cocotb.start_soon(self._process_write_resp())
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cocotb.start_soon(self._run())
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def set_pause_generator(self, generator=None):
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if self._pause_cr is not None:
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self._pause_cr.kill()
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self._pause_cr = None
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self._pause_generator = generator
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if self._pause_generator is not None:
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self._pause_cr = cocotb.start_soon(self._run_pause())
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def clear_pause_generator(self):
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self.set_pause_generator(None)
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def idle(self):
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return not self.in_flight_operations
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async def wait(self):
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while not self.idle():
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await self._idle.wait()
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async def write(self, address, data):
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if address < 0 or address >= 2**self.address_width:
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raise ValueError("Address out of range")
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if isinstance(data, int):
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raise ValueError("Expected bytes or bytearray for data")
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if address+len(data) > 2**self.address_width:
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raise ValueError("Requested transfer overruns end of address space")
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event = Event()
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data = bytes(data)
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self.in_flight_operations += 1
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self._idle.clear()
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await self.write_command_queue.put(WriteCmd(address, data, event))
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await event.wait()
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return event.data
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async def _process_write(self):
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while True:
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cmd = await self.write_command_queue.get()
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self.current_write_command = cmd
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seg_start_offset = cmd.address % self.seg_byte_lanes
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seg_end_offset = ((cmd.address + len(cmd.data) - 1) % self.seg_byte_lanes) + 1
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seg_be_start = (self.seg_be_mask << seg_start_offset) & self.seg_be_mask
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seg_be_end = self.seg_be_mask >> (self.seg_byte_lanes - seg_end_offset)
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first_seg = (cmd.address // self.seg_byte_lanes) % self.seg_count
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segments = (len(cmd.data) + (cmd.address % self.seg_byte_lanes) + self.seg_byte_lanes-1) // self.seg_byte_lanes
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resp_cmd = WriteRespCmd(cmd.address, len(cmd.data), segments, first_seg, cmd.event)
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await self.int_write_resp_command_queue.put(resp_cmd)
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offset = 0
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Write start addr: 0x%08x data: %s",
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cmd.address, ' '.join((f'{c:02x}' for c in cmd.data)))
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seg = first_seg
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for k in range(segments):
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start = 0
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stop = self.seg_byte_lanes
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be = self.seg_be_mask
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if k == 0:
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start = seg_start_offset
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be &= seg_be_start
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if k == segments-1:
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stop = seg_end_offset
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be &= seg_be_end
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val = 0
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for j in range(start, stop):
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val |= cmd.data[offset] << j*8
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offset += 1
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op = SegWriteData()
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op.addr = (cmd.address + k*self.seg_byte_lanes) // self.byte_lanes
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op.data = val
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op.be = be
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await self.seg_write_queue[seg].put(op)
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seg = (seg + 1) % self.seg_count
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self.current_write_command = None
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async def _process_write_resp(self):
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while True:
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cmd = await self.int_write_resp_command_queue.get()
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self.current_write_resp_command = cmd
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seg = cmd.first_seg
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for k in range(cmd.segments):
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await self.seg_write_resp_queue[seg].get()
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seg = (seg + 1) % self.seg_count
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Write complete addr: 0x%08x length: %d", cmd.address, cmd.length)
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write_resp = WriteResp(cmd.address, cmd.length)
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cmd.event.set(write_resp)
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self.current_write_resp_command = None
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self.in_flight_operations -= 1
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if self.in_flight_operations == 0:
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self._idle.set()
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async def _run(self):
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cmd_valid = 0
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cmd_addr = 0
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cmd_data = 0
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cmd_be = 0
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clock_edge_event = RisingEdge(self.clock)
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while True:
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await clock_edge_event
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cmd_ready_sample = self.bus.wr_cmd_ready.value
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done_sample = self.bus.wr_done.value
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if self.reset is not None and self.reset.value:
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self.bus.wr_cmd_valid.setimmediatevalue(0)
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continue
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# process segments
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for seg in range(self.seg_count):
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seg_mask = 1 << seg
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if (cmd_ready_sample & seg_mask) or not (cmd_valid & seg_mask):
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if not self.seg_write_queue[seg].empty() and not self.pause:
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op = await self.seg_write_queue[seg].get()
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cmd_addr &= ~(self.seg_addr_mask << self.seg_addr_width*seg)
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cmd_addr |= ((op.addr & self.seg_addr_mask) << self.seg_addr_width*seg)
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cmd_data &= ~(self.seg_data_mask << self.seg_data_width*seg)
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cmd_data |= ((op.data & self.seg_data_mask) << self.seg_data_width*seg)
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cmd_be &= ~(self.seg_be_mask << self.seg_be_width*seg)
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cmd_be |= ((op.be & self.seg_be_mask) << self.seg_be_width*seg)
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cmd_valid |= seg_mask
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Write word seg: %d addr: 0x%08x be 0x%02x data %s",
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seg, op.addr, op.be, ' '.join((f'{c:02x}' for c in op.data.to_bytes(self.seg_byte_lanes, 'little'))))
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else:
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cmd_valid &= ~seg_mask
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if done_sample & seg_mask:
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await self.seg_write_resp_queue[seg].put(None)
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self.bus.wr_cmd_valid.value = cmd_valid
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self.bus.wr_cmd_addr.value = cmd_addr
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self.bus.wr_cmd_data.value = cmd_data
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self.bus.wr_cmd_be.value = cmd_be
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async def _run_pause(self):
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clock_edge_event = RisingEdge(self.clock)
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for val in self._pause_generator:
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self.pause = val
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await clock_edge_event
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class PsdpRamMasterRead(Region):
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def __init__(self, bus, clock, reset=None, **kwargs):
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self.bus = bus
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self.clock = clock
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self.reset = reset
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if bus._name:
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
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else:
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self.log = logging.getLogger(f"cocotb.{bus._entity._name}")
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self.log.info("Parallel Simple Dual Port RAM master model (read)")
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.pause = False
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self._pause_generator = None
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self._pause_cr = None
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self.in_flight_operations = 0
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self._idle = Event()
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self._idle.set()
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self.width = len(self.bus.rd_resp_data)
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.seg_count = len(self.bus.rd_cmd_valid)
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self.seg_data_width = self.width // self.seg_count
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self.seg_byte_lanes = self.seg_data_width // self.byte_size
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self.seg_addr_width = len(self.bus.rd_cmd_addr) // self.seg_count
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self.seg_data_mask = 2**self.seg_data_width-1
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self.seg_addr_mask = 2**self.seg_addr_width-1
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self.address_width = self.seg_addr_width + (self.seg_byte_lanes*self.seg_count-1).bit_length()
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self.read_command_queue = Queue()
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self.read_command_queue.queue_occupancy_limit = 2
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self.current_read_command = None
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self.seg_read_queue = [Queue() for x in range(self.seg_count)]
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self.seg_read_resp_queue = [Queue() for x in range(self.seg_count)]
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self.int_read_resp_command_queue = Queue()
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self.current_read_resp_command = None
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super().__init__(2**self.address_width, **kwargs)
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self.log.info("Parallel Simple Dual Port RAM master model configuration:")
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self.log.info(" Address width: %d bits", self.address_width)
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self.log.info(" Segment count: %d", self.seg_count)
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self.log.info(" Segment addr width: %d bits", self.seg_addr_width)
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self.log.info(" Segment data width: %d bits (%d bytes)", self.seg_data_width, self.seg_byte_lanes)
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self.log.info(" Total data width: %d bits (%d bytes)", self.width, self.byte_lanes)
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self.bus.rd_cmd_valid.setimmediatevalue(0)
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self.bus.rd_resp_ready.setimmediatevalue(0)
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cocotb.start_soon(self._process_read())
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cocotb.start_soon(self._process_read_resp())
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cocotb.start_soon(self._run())
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def set_pause_generator(self, generator=None):
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if self._pause_cr is not None:
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self._pause_cr.kill()
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self._pause_cr = None
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self._pause_generator = generator
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if self._pause_generator is not None:
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self._pause_cr = cocotb.start_soon(self._run_pause())
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def clear_pause_generator(self):
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self.set_pause_generator(None)
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def idle(self):
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return not self.in_flight_operations
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async def wait(self):
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while not self.idle():
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await self._idle.wait()
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async def read(self, address, length):
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if address < 0 or address >= 2**self.address_width:
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raise ValueError("Address out of range")
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if length < 0:
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raise ValueError("Read length must be positive")
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if address+length > 2**self.address_width:
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raise ValueError("Requested transfer overruns end of address space")
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event = Event()
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self.in_flight_operations += 1
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self._idle.clear()
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await self.read_command_queue.put(ReadCmd(address, length, event))
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await event.wait()
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return event.data
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async def _process_read(self):
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while True:
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cmd = await self.read_command_queue.get()
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self.current_read_command = cmd
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first_seg = (cmd.address // self.seg_byte_lanes) % self.seg_count
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segments = (cmd.length + (cmd.address % self.seg_byte_lanes) + self.seg_byte_lanes-1) // self.seg_byte_lanes
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resp_cmd = ReadRespCmd(cmd.address, cmd.length, segments, first_seg, cmd.event)
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await self.int_read_resp_command_queue.put(resp_cmd)
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if self.log.isEnabledFor(logging.INFO):
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self.log.info("Read start addr: 0x%08x length: %d", cmd.address, cmd.length)
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seg = first_seg
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for k in range(segments):
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op = SegReadCmd()
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op.addr = (cmd.address + k*self.seg_byte_lanes) // self.byte_lanes
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await self.seg_read_queue[seg].put(op)
|
|
|
|
seg = (seg + 1) % self.seg_count
|
|
|
|
self.current_read_command = None
|
|
|
|
async def _process_read_resp(self):
|
|
while True:
|
|
cmd = await self.int_read_resp_command_queue.get()
|
|
self.current_read_resp_command = cmd
|
|
|
|
seg_start_offset = cmd.address % self.seg_byte_lanes
|
|
seg_end_offset = ((cmd.address + cmd.length - 1) % self.seg_byte_lanes) + 1
|
|
|
|
data = bytearray()
|
|
|
|
seg = cmd.first_seg
|
|
for k in range(cmd.segments):
|
|
seg_data = await self.seg_read_resp_queue[seg].get()
|
|
|
|
start = 0
|
|
stop = self.seg_byte_lanes
|
|
|
|
if k == 0:
|
|
start = seg_start_offset
|
|
if k == cmd.segments-1:
|
|
stop = seg_end_offset
|
|
|
|
for j in range(start, stop):
|
|
data.extend(bytearray([(seg_data >> j*8) & 0xff]))
|
|
|
|
seg = (seg + 1) % self.seg_count
|
|
|
|
if self.log.isEnabledFor(logging.INFO):
|
|
self.log.info("Read complete addr: 0x%08x data: %s",
|
|
cmd.address, ' '.join((f'{c:02x}' for c in data)))
|
|
|
|
read_resp = ReadResp(cmd.address, bytes(data))
|
|
|
|
cmd.event.set(read_resp)
|
|
|
|
self.current_read_resp_command = None
|
|
|
|
self.in_flight_operations -= 1
|
|
|
|
if self.in_flight_operations == 0:
|
|
self._idle.set()
|
|
|
|
async def _run(self):
|
|
cmd_valid = 0
|
|
cmd_addr = 0
|
|
resp_ready = 0
|
|
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
while True:
|
|
await clock_edge_event
|
|
|
|
cmd_ready_sample = self.bus.rd_cmd_ready.value
|
|
resp_valid_sample = self.bus.rd_resp_valid.value
|
|
|
|
if resp_valid_sample:
|
|
resp_data_sample = self.bus.rd_resp_data.value
|
|
|
|
if self.reset is not None and self.reset.value:
|
|
self.bus.rd_cmd_valid.setimmediatevalue(0)
|
|
self.bus.rd_resp_ready.setimmediatevalue(0)
|
|
cmd_valid = 0
|
|
resp_ready = 0
|
|
continue
|
|
|
|
# process segments
|
|
for seg in range(self.seg_count):
|
|
seg_mask = 1 << seg
|
|
|
|
if (cmd_ready_sample & seg_mask) or not (cmd_valid & seg_mask):
|
|
if not self.seg_read_queue[seg].empty() and not self.pause:
|
|
op = await self.seg_read_queue[seg].get()
|
|
cmd_addr &= ~(self.seg_addr_mask << self.seg_addr_width*seg)
|
|
cmd_addr |= ((op.addr & self.seg_addr_mask) << self.seg_addr_width*seg)
|
|
cmd_valid |= seg_mask
|
|
|
|
if self.log.isEnabledFor(logging.INFO):
|
|
self.log.info("Read word seg: %d addr: 0x%08x", seg, op.addr)
|
|
else:
|
|
cmd_valid &= ~seg_mask
|
|
|
|
if resp_ready & resp_valid_sample & (1 << seg):
|
|
seg_data = (resp_data_sample >> self.seg_data_width*seg) & self.seg_data_mask
|
|
|
|
await self.seg_read_resp_queue[seg].put(seg_data)
|
|
|
|
resp_ready = 2**self.seg_count-1
|
|
|
|
if self.pause:
|
|
resp_ready = 0
|
|
|
|
self.bus.rd_cmd_valid.value = cmd_valid
|
|
self.bus.rd_cmd_addr.value = cmd_addr
|
|
|
|
self.bus.rd_resp_ready.value = resp_ready
|
|
|
|
async def _run_pause(self):
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
for val in self._pause_generator:
|
|
self.pause = val
|
|
await clock_edge_event
|
|
|
|
|
|
class PsdpRamMaster(Region):
|
|
def __init__(self, bus, clock, reset=None, **kwargs):
|
|
self.write_if = None
|
|
self.read_if = None
|
|
|
|
self.write_if = PsdpRamMasterWrite(bus.write, clock, reset)
|
|
self.read_if = PsdpRamMasterRead(bus.read, clock, reset)
|
|
|
|
super().__init__(max(self.write_if.size, self.read_if.size), **kwargs)
|
|
|
|
def init_read(self, address, length, event=None):
|
|
return self.read_if.init_read(address, length, event)
|
|
|
|
def init_write(self, address, data, event=None):
|
|
return self.write_if.init_write(address, data, event)
|
|
|
|
def idle(self):
|
|
return (not self.read_if or self.read_if.idle()) and (not self.write_if or self.write_if.idle())
|
|
|
|
async def wait(self):
|
|
while not self.idle():
|
|
await self.write_if.wait()
|
|
await self.read_if.wait()
|
|
|
|
async def wait_read(self):
|
|
await self.read_if.wait()
|
|
|
|
async def wait_write(self):
|
|
await self.write_if.wait()
|
|
|
|
async def read(self, address, length):
|
|
return await self.read_if.read(address, length)
|
|
|
|
async def write(self, address, data):
|
|
return await self.write_if.write(address, data)
|
|
|
|
|
|
class PsdpRamWrite(Memory):
|
|
|
|
def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
|
|
self.bus = bus
|
|
self.clock = clock
|
|
self.reset = reset
|
|
self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
|
|
|
|
self.log.info("Parallel Simple Dual Port RAM model (write)")
|
|
self.log.info("Copyright (c) 2020 Alex Forencich")
|
|
|
|
super().__init__(size, mem, *args, **kwargs)
|
|
|
|
self.pause = False
|
|
self._pause_generator = None
|
|
self._pause_cr = None
|
|
|
|
self.width = len(self.bus.wr_cmd_data)
|
|
self.byte_size = 8
|
|
self.byte_lanes = len(self.bus.wr_cmd_be)
|
|
|
|
self.seg_count = len(self.bus.wr_cmd_valid)
|
|
self.seg_data_width = self.width // self.seg_count
|
|
self.seg_byte_lanes = self.seg_data_width // self.byte_size
|
|
self.seg_addr_width = len(self.bus.wr_cmd_addr) // self.seg_count
|
|
self.seg_be_width = self.seg_data_width // self.byte_size
|
|
|
|
self.seg_data_mask = 2**self.seg_data_width-1
|
|
self.seg_addr_mask = 2**self.seg_addr_width-1
|
|
self.seg_be_mask = 2**self.seg_be_width-1
|
|
|
|
self.log.info("Parallel Simple Dual Port RAM model configuration:")
|
|
self.log.info(" Memory size: %d bytes", len(self.mem))
|
|
self.log.info(" Segment count: %d", self.seg_count)
|
|
self.log.info(" Segment addr width: %d bits", self.seg_addr_width)
|
|
self.log.info(" Segment data width: %d bits (%d bytes)", self.seg_data_width, self.seg_byte_lanes)
|
|
self.log.info(" Total data width: %d bits (%d bytes)", self.width, self.byte_lanes)
|
|
|
|
assert self.seg_be_width*self.seg_count == len(self.bus.wr_cmd_be)
|
|
|
|
self.bus.wr_cmd_ready.setimmediatevalue(0)
|
|
self.bus.wr_done.setimmediatevalue(0)
|
|
|
|
cocotb.start_soon(self._run())
|
|
|
|
def set_pause_generator(self, generator=None):
|
|
if self._pause_cr is not None:
|
|
self._pause_cr.kill()
|
|
self._pause_cr = None
|
|
|
|
self._pause_generator = generator
|
|
|
|
if self._pause_generator is not None:
|
|
self._pause_cr = cocotb.start_soon(self._run_pause())
|
|
|
|
def clear_pause_generator(self):
|
|
self.set_pause_generator(None)
|
|
|
|
async def _run(self):
|
|
cmd_ready = 0
|
|
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
while True:
|
|
await clock_edge_event
|
|
|
|
wr_done = 0
|
|
|
|
cmd_valid_sample = self.bus.wr_cmd_valid.value
|
|
|
|
if cmd_valid_sample:
|
|
cmd_be_sample = self.bus.wr_cmd_be.value
|
|
cmd_addr_sample = self.bus.wr_cmd_addr.value
|
|
cmd_data_sample = self.bus.wr_cmd_data.value
|
|
|
|
if self.reset is not None and self.reset.value:
|
|
self.bus.wr_cmd_ready.setimmediatevalue(0)
|
|
self.bus.wr_done.setimmediatevalue(0)
|
|
continue
|
|
|
|
# process segments
|
|
for seg in range(self.seg_count):
|
|
if cmd_ready & cmd_valid_sample & (1 << seg):
|
|
seg_addr = (cmd_addr_sample >> self.seg_addr_width*seg) & self.seg_addr_mask
|
|
seg_data = (cmd_data_sample >> self.seg_data_width*seg) & self.seg_data_mask
|
|
seg_be = (cmd_be_sample >> self.seg_be_width*seg) & self.seg_be_mask
|
|
|
|
addr = (seg_addr*self.seg_count+seg)*self.seg_byte_lanes
|
|
|
|
# generate operation list
|
|
offset = 0
|
|
start_offset = None
|
|
write_ops = []
|
|
|
|
data = seg_data.to_bytes(self.seg_byte_lanes, 'little')
|
|
|
|
for i in range(self.byte_lanes):
|
|
if seg_be & (1 << i):
|
|
if start_offset is None:
|
|
start_offset = offset
|
|
else:
|
|
if start_offset is not None and offset != start_offset:
|
|
write_ops.append((addr+start_offset, data[start_offset:offset]))
|
|
start_offset = None
|
|
|
|
offset += 1
|
|
|
|
if start_offset is not None and offset != start_offset:
|
|
write_ops.append((addr+start_offset, data[start_offset:offset]))
|
|
|
|
# perform writes
|
|
for addr, data in write_ops:
|
|
self.write(addr, data)
|
|
|
|
wr_done |= 1 << seg
|
|
|
|
self.log.info("Write word seg: %d addr: 0x%08x be 0x%02x data %s",
|
|
seg, addr, seg_be, ' '.join((f'{c:02x}' for c in data)))
|
|
|
|
cmd_ready = 2**self.seg_count-1
|
|
|
|
if self.pause:
|
|
cmd_ready = 0
|
|
|
|
self.bus.wr_cmd_ready.value = cmd_ready
|
|
self.bus.wr_done.value = wr_done
|
|
|
|
async def _run_pause(self):
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
for val in self._pause_generator:
|
|
self.pause = val
|
|
await clock_edge_event
|
|
|
|
|
|
class PsdpRamRead(Memory):
|
|
|
|
def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
|
|
self.bus = bus
|
|
self.clock = clock
|
|
self.reset = reset
|
|
self.log = logging.getLogger(f"cocotb.{bus._entity._name}.{bus._name}")
|
|
|
|
self.log.info("Parallel Simple Dual Port RAM model (read)")
|
|
self.log.info("Copyright (c) 2020 Alex Forencich")
|
|
|
|
super().__init__(size, mem, *args, **kwargs)
|
|
|
|
self.pause = False
|
|
self._pause_generator = None
|
|
self._pause_cr = None
|
|
|
|
self.width = len(self.bus.rd_resp_data)
|
|
self.byte_size = 8
|
|
self.byte_lanes = self.width // self.byte_size
|
|
|
|
self.seg_count = len(self.bus.rd_cmd_valid)
|
|
self.seg_data_width = self.width // self.seg_count
|
|
self.seg_byte_lanes = self.seg_data_width // self.byte_size
|
|
self.seg_addr_width = len(self.bus.rd_cmd_addr) // self.seg_count
|
|
|
|
self.seg_data_mask = 2**self.seg_data_width-1
|
|
self.seg_addr_mask = 2**self.seg_addr_width-1
|
|
|
|
self.log.info("Parallel Simple Dual Port RAM model configuration:")
|
|
self.log.info(" Memory size: %d bytes", len(self.mem))
|
|
self.log.info(" Segment count: %d", self.seg_count)
|
|
self.log.info(" Segment addr width: %d bits", self.seg_addr_width)
|
|
self.log.info(" Segment data width: %d bits (%d bytes)", self.seg_data_width, self.seg_byte_lanes)
|
|
self.log.info(" Total data width: %d bits (%d bytes)", self.width, self.byte_lanes)
|
|
|
|
self.bus.rd_cmd_ready.setimmediatevalue(0)
|
|
self.bus.rd_resp_valid.setimmediatevalue(0)
|
|
|
|
cocotb.start_soon(self._run())
|
|
|
|
def set_pause_generator(self, generator=None):
|
|
if self._pause_cr is not None:
|
|
self._pause_cr.kill()
|
|
self._pause_cr = None
|
|
|
|
self._pause_generator = generator
|
|
|
|
if self._pause_generator is not None:
|
|
self._pause_cr = cocotb.start_soon(self._run_pause())
|
|
|
|
def clear_pause_generator(self):
|
|
self.set_pause_generator(None)
|
|
|
|
async def _run(self):
|
|
pipeline = [[None for x in range(1)] for seg in range(self.seg_count)]
|
|
|
|
cmd_ready = 0
|
|
resp_valid = 0
|
|
resp_data = 0
|
|
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
while True:
|
|
await clock_edge_event
|
|
|
|
cmd_valid_sample = self.bus.rd_cmd_valid.value
|
|
|
|
if cmd_valid_sample:
|
|
cmd_addr_sample = self.bus.rd_cmd_addr.value
|
|
|
|
resp_ready_sample = self.bus.rd_resp_ready.value
|
|
|
|
if self.reset is not None and self.reset.value:
|
|
self.bus.rd_cmd_ready.setimmediatevalue(0)
|
|
self.bus.rd_resp_valid.setimmediatevalue(0)
|
|
cmd_ready = 0
|
|
resp_valid = 0
|
|
continue
|
|
|
|
# process segments
|
|
for seg in range(self.seg_count):
|
|
seg_mask = 1 << seg
|
|
|
|
if (resp_ready_sample & seg_mask) or not (resp_valid & seg_mask):
|
|
if pipeline[seg][-1] is not None:
|
|
resp_data &= ~(self.seg_data_mask << self.seg_data_width*seg)
|
|
resp_data |= ((pipeline[seg][-1] & self.seg_data_mask) << self.seg_data_width*seg)
|
|
resp_valid |= seg_mask
|
|
pipeline[seg][-1] = None
|
|
else:
|
|
resp_valid &= ~seg_mask
|
|
|
|
for i in range(len(pipeline[seg])-1, 0, -1):
|
|
if pipeline[seg][i] is None:
|
|
pipeline[i] = pipeline[i-1]
|
|
pipeline[i-1] = None
|
|
|
|
if cmd_ready & cmd_valid_sample & seg_mask:
|
|
seg_addr = (cmd_addr_sample >> self.seg_addr_width*seg) & self.seg_addr_mask
|
|
|
|
addr = (seg_addr*self.seg_count+seg)*self.seg_byte_lanes
|
|
|
|
data = self.read(addr % self.size, self.seg_byte_lanes)
|
|
pipeline[seg][0] = int.from_bytes(data, 'little')
|
|
|
|
self.log.info("Read word seg: %d addr: 0x%08x data %s",
|
|
seg, addr, ' '.join((f'{c:02x}' for c in data)))
|
|
|
|
if (not resp_valid & seg_mask) or None in pipeline[seg]:
|
|
cmd_ready |= seg_mask
|
|
else:
|
|
cmd_ready &= ~seg_mask
|
|
|
|
if self.pause:
|
|
cmd_ready = 0
|
|
|
|
self.bus.rd_cmd_ready.value = cmd_ready
|
|
|
|
self.bus.rd_resp_data.value = resp_data
|
|
self.bus.rd_resp_valid.value = resp_valid
|
|
|
|
async def _run_pause(self):
|
|
clock_edge_event = RisingEdge(self.clock)
|
|
|
|
for val in self._pause_generator:
|
|
self.pause = val
|
|
await clock_edge_event
|
|
|
|
|
|
class PsdpRam(Memory):
|
|
def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
|
|
self.write_if = None
|
|
self.read_if = None
|
|
|
|
super().__init__(size, mem, *args, **kwargs)
|
|
|
|
self.write_if = PsdpRamWrite(bus.write, clock, reset, mem=self.mem)
|
|
self.read_if = PsdpRamRead(bus.read, clock, reset, mem=self.mem)
|