mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
913 lines
23 KiB
Verilog
913 lines
23 KiB
Verilog
/*
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Copyright (c) 2014-2021 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga (
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/*
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* Reset: Push button, active low
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*/
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input wire reset,
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/*
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* GPIO
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*/
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input wire [3:0] sw,
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output wire [2:0] led,
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/*
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* I2C for board management
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*/
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inout wire i2c_scl,
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inout wire i2c_sda,
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/*
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* Ethernet: QSFP28
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*/
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output wire qsfp0_tx1_p,
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output wire qsfp0_tx1_n,
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input wire qsfp0_rx1_p,
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input wire qsfp0_rx1_n,
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output wire qsfp0_tx2_p,
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output wire qsfp0_tx2_n,
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input wire qsfp0_rx2_p,
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input wire qsfp0_rx2_n,
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output wire qsfp0_tx3_p,
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output wire qsfp0_tx3_n,
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input wire qsfp0_rx3_p,
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input wire qsfp0_rx3_n,
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output wire qsfp0_tx4_p,
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output wire qsfp0_tx4_n,
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input wire qsfp0_rx4_p,
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input wire qsfp0_rx4_n,
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// input wire qsfp0_mgt_refclk_0_p,
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// input wire qsfp0_mgt_refclk_0_n,
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input wire qsfp0_mgt_refclk_1_p,
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input wire qsfp0_mgt_refclk_1_n,
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output wire qsfp0_modsell,
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output wire qsfp0_resetl,
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input wire qsfp0_modprsl,
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input wire qsfp0_intl,
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output wire qsfp0_lpmode,
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output wire qsfp0_refclk_reset,
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output wire [1:0] qsfp0_fs,
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output wire qsfp1_tx1_p,
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output wire qsfp1_tx1_n,
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input wire qsfp1_rx1_p,
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input wire qsfp1_rx1_n,
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output wire qsfp1_tx2_p,
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output wire qsfp1_tx2_n,
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input wire qsfp1_rx2_p,
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input wire qsfp1_rx2_n,
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output wire qsfp1_tx3_p,
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output wire qsfp1_tx3_n,
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input wire qsfp1_rx3_p,
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input wire qsfp1_rx3_n,
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output wire qsfp1_tx4_p,
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output wire qsfp1_tx4_n,
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input wire qsfp1_rx4_p,
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input wire qsfp1_rx4_n,
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// input wire qsfp1_mgt_refclk_0_p,
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// input wire qsfp1_mgt_refclk_0_n,
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input wire qsfp1_mgt_refclk_1_p,
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input wire qsfp1_mgt_refclk_1_n,
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output wire qsfp1_modsell,
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output wire qsfp1_resetl,
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input wire qsfp1_modprsl,
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input wire qsfp1_intl,
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output wire qsfp1_lpmode,
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output wire qsfp1_refclk_reset,
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output wire [1:0] qsfp1_fs,
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/*
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* UART: 500000 bps, 8N1
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*/
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output wire uart_rxd,
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input wire uart_txd
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);
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// Clock and reset
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wire cfgmclk_int;
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wire clk_161mhz_ref_int;
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// Internal 125 MHz clock
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wire clk_125mhz_mmcm_out;
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wire clk_125mhz_int;
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wire rst_125mhz_int;
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// Internal 156.25 MHz clock
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wire clk_156mhz_int;
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wire rst_156mhz_int;
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wire mmcm_rst;
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wire mmcm_locked;
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wire mmcm_clkfb;
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// MMCM instance
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// 161.13 MHz in, 125 MHz out
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// PFD range: 10 MHz to 500 MHz
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// VCO range: 800 MHz to 1600 MHz
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// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
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// Divide by 7.5 to get output frequency of 125 MHz
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MMCME4_BASE #(
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.BANDWIDTH("OPTIMIZED"),
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.CLKOUT0_DIVIDE_F(7.5),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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.CLKOUT1_DIVIDE(1),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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.CLKFBOUT_MULT_F(64),
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.CLKFBOUT_PHASE(0),
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.DIVCLK_DIVIDE(11),
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.REF_JITTER1(0.010),
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.CLKIN1_PERIOD(6.206),
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.STARTUP_WAIT("FALSE"),
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.CLKOUT4_CASCADE("FALSE")
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)
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clk_mmcm_inst (
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.CLKIN1(clk_161mhz_ref_int),
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.CLKFBIN(mmcm_clkfb),
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.RST(mmcm_rst),
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.PWRDWN(1'b0),
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.CLKOUT0(clk_125mhz_mmcm_out),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_125mhz_bufg_inst (
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.I(clk_125mhz_mmcm_out),
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.O(clk_125mhz_int)
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);
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sync_reset #(
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.N(4)
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)
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sync_reset_125mhz_inst (
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.clk(clk_125mhz_int),
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.rst(~mmcm_locked),
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.out(rst_125mhz_int)
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);
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// GPIO
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wire [3:0] sw_int;
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debounce_switch #(
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.WIDTH(4),
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.N(4),
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.RATE(156000)
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)
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debounce_switch_inst (
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.clk(clk_156mhz_int),
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.rst(rst_156mhz_int),
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.in({sw}),
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.out({sw_int})
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);
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wire uart_txd_int;
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sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_156mhz_int),
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.in({uart_txd}),
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.out({uart_txd_int})
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);
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// SI570 I2C
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wire i2c_scl_i;
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wire i2c_scl_o = 1'b1;
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wire i2c_scl_t = 1'b1;
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wire i2c_sda_i;
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wire i2c_sda_o = 1'b1;
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wire i2c_sda_t = 1'b1;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
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// startupe3 instance
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wire cfgmclk;
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STARTUPE3
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startupe3_inst (
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.CFGCLK(),
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.CFGMCLK(cfgmclk),
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.DI(4'd0),
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.DO(),
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.DTS(1'b1),
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.EOS(),
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.FCSBO(1'b0),
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.FCSBTS(1'b1),
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.GSR(1'b0),
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.GTS(1'b0),
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.KEYCLEARB(1'b1),
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.PACK(1'b0),
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.PREQ(),
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.USRCCLKO(1'b0),
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.USRCCLKTS(1'b1),
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.USRDONEO(1'b0),
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.USRDONETS(1'b1)
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);
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BUFG
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cfgmclk_bufg_inst (
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.I(cfgmclk),
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.O(cfgmclk_int)
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);
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// configure SI5335 clock generators
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reg qsfp_refclk_reset_reg = 1'b1;
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reg sys_reset_reg = 1'b1;
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reg [9:0] reset_timer_reg = 0;
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assign mmcm_rst = sys_reset_reg;
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always @(posedge cfgmclk_int) begin
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if (&reset_timer_reg) begin
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if (qsfp_refclk_reset_reg) begin
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qsfp_refclk_reset_reg <= 1'b0;
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reset_timer_reg <= 0;
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end else begin
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qsfp_refclk_reset_reg <= 1'b0;
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sys_reset_reg <= 1'b0;
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end
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end else begin
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reset_timer_reg <= reset_timer_reg + 1;
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end
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if (!reset) begin
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qsfp_refclk_reset_reg <= 1'b1;
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sys_reset_reg <= 1'b1;
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reset_timer_reg <= 0;
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end
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end
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// XGMII 10G PHY
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// QSFP0
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assign qsfp0_modsell = 1'b0;
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assign qsfp0_resetl = 1'b1;
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assign qsfp0_lpmode = 1'b0;
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assign qsfp0_refclk_reset = qsfp_refclk_reset_reg;
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assign qsfp0_fs = 2'b10;
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wire qsfp0_tx_clk_1_int;
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wire qsfp0_tx_rst_1_int;
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wire [63:0] qsfp0_txd_1_int;
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wire [7:0] qsfp0_txc_1_int;
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wire qsfp0_rx_clk_1_int;
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wire qsfp0_rx_rst_1_int;
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wire [63:0] qsfp0_rxd_1_int;
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wire [7:0] qsfp0_rxc_1_int;
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wire qsfp0_tx_clk_2_int;
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wire qsfp0_tx_rst_2_int;
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wire [63:0] qsfp0_txd_2_int;
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wire [7:0] qsfp0_txc_2_int;
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wire qsfp0_rx_clk_2_int;
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wire qsfp0_rx_rst_2_int;
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wire [63:0] qsfp0_rxd_2_int;
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wire [7:0] qsfp0_rxc_2_int;
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wire qsfp0_tx_clk_3_int;
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wire qsfp0_tx_rst_3_int;
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wire [63:0] qsfp0_txd_3_int;
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wire [7:0] qsfp0_txc_3_int;
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wire qsfp0_rx_clk_3_int;
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wire qsfp0_rx_rst_3_int;
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wire [63:0] qsfp0_rxd_3_int;
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wire [7:0] qsfp0_rxc_3_int;
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wire qsfp0_tx_clk_4_int;
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wire qsfp0_tx_rst_4_int;
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wire [63:0] qsfp0_txd_4_int;
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wire [7:0] qsfp0_txc_4_int;
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wire qsfp0_rx_clk_4_int;
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wire qsfp0_rx_rst_4_int;
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wire [63:0] qsfp0_rxd_4_int;
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wire [7:0] qsfp0_rxc_4_int;
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assign clk_156mhz_int = qsfp0_tx_clk_1_int;
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assign rst_156mhz_int = qsfp0_tx_rst_1_int;
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wire qsfp0_rx_block_lock_1;
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wire qsfp0_rx_block_lock_2;
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wire qsfp0_rx_block_lock_3;
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wire qsfp0_rx_block_lock_4;
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wire qsfp0_gtpowergood;
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wire qsfp0_mgt_refclk_1;
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wire qsfp0_mgt_refclk_1_int;
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wire qsfp0_mgt_refclk_1_bufg;
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assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
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IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
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.I (qsfp0_mgt_refclk_1_p),
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.IB (qsfp0_mgt_refclk_1_n),
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.CEB (1'b0),
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.O (qsfp0_mgt_refclk_1),
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.ODIV2 (qsfp0_mgt_refclk_1_int)
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);
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BUFG_GT bufg_gt_refclk_inst (
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.CE (qsfp0_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp0_mgt_refclk_1_int),
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.O (qsfp0_mgt_refclk_1_bufg)
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);
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wire qsfp0_qpll0lock;
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wire qsfp0_qpll0outclk;
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wire qsfp0_qpll0outrefclk;
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(1)
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)
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qsfp0_phy_1_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(qsfp0_gtpowergood),
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// PLL out
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.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
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.xcvr_qpll0lock_out(qsfp0_qpll0lock),
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.xcvr_qpll0outclk_out(qsfp0_qpll0outclk),
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.xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk),
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// PLL in
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.xcvr_qpll0lock_in(1'b0),
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.xcvr_qpll0reset_out(),
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.xcvr_qpll0clk_in(1'b0),
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.xcvr_qpll0refclk_in(1'b0),
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// Serial data
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.xcvr_txp(qsfp0_tx1_p),
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.xcvr_txn(qsfp0_tx1_n),
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.xcvr_rxp(qsfp0_rx1_p),
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.xcvr_rxn(qsfp0_rx1_n),
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// PHY connections
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.phy_tx_clk(qsfp0_tx_clk_1_int),
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.phy_tx_rst(qsfp0_tx_rst_1_int),
|
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.phy_xgmii_txd(qsfp0_txd_1_int),
|
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.phy_xgmii_txc(qsfp0_txc_1_int),
|
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.phy_rx_clk(qsfp0_rx_clk_1_int),
|
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.phy_rx_rst(qsfp0_rx_rst_1_int),
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.phy_xgmii_rxd(qsfp0_rxd_1_int),
|
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.phy_xgmii_rxc(qsfp0_rxc_1_int),
|
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.phy_tx_bad_block(),
|
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.phy_rx_error_count(),
|
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.phy_rx_bad_block(),
|
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.phy_rx_sequence_error(),
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.phy_rx_block_lock(qsfp0_rx_block_lock_1),
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.phy_rx_high_ber(),
|
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.phy_tx_prbs31_enable(),
|
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.phy_rx_prbs31_enable()
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);
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|
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eth_xcvr_phy_wrapper #(
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.HAS_COMMON(0)
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)
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qsfp0_phy_2_inst (
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.xcvr_ctrl_clk(clk_125mhz_int),
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.xcvr_ctrl_rst(rst_125mhz_int),
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// Common
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.xcvr_gtpowergood_out(),
|
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// PLL out
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.xcvr_gtrefclk00_in(1'b0),
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.xcvr_qpll0lock_out(),
|
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.xcvr_qpll0outclk_out(),
|
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.xcvr_qpll0outrefclk_out(),
|
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|
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// PLL in
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.xcvr_qpll0lock_in(qsfp0_qpll0lock),
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.xcvr_qpll0reset_out(),
|
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.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
|
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.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
|
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|
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// Serial data
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.xcvr_txp(qsfp0_tx2_p),
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.xcvr_txn(qsfp0_tx2_n),
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.xcvr_rxp(qsfp0_rx2_p),
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.xcvr_rxn(qsfp0_rx2_n),
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|
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// PHY connections
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.phy_tx_clk(qsfp0_tx_clk_2_int),
|
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.phy_tx_rst(qsfp0_tx_rst_2_int),
|
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.phy_xgmii_txd(qsfp0_txd_2_int),
|
|
.phy_xgmii_txc(qsfp0_txc_2_int),
|
|
.phy_rx_clk(qsfp0_rx_clk_2_int),
|
|
.phy_rx_rst(qsfp0_rx_rst_2_int),
|
|
.phy_xgmii_rxd(qsfp0_rxd_2_int),
|
|
.phy_xgmii_rxc(qsfp0_rxc_2_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0)
|
|
)
|
|
qsfp0_phy_3_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp0_tx3_p),
|
|
.xcvr_txn(qsfp0_tx3_n),
|
|
.xcvr_rxp(qsfp0_rx3_p),
|
|
.xcvr_rxn(qsfp0_rx3_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp0_tx_clk_3_int),
|
|
.phy_tx_rst(qsfp0_tx_rst_3_int),
|
|
.phy_xgmii_txd(qsfp0_txd_3_int),
|
|
.phy_xgmii_txc(qsfp0_txc_3_int),
|
|
.phy_rx_clk(qsfp0_rx_clk_3_int),
|
|
.phy_rx_rst(qsfp0_rx_rst_3_int),
|
|
.phy_xgmii_rxd(qsfp0_rxd_3_int),
|
|
.phy_xgmii_rxc(qsfp0_rxc_3_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0)
|
|
)
|
|
qsfp0_phy_4_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp0_tx4_p),
|
|
.xcvr_txn(qsfp0_tx4_n),
|
|
.xcvr_rxp(qsfp0_rx4_p),
|
|
.xcvr_rxn(qsfp0_rx4_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp0_tx_clk_4_int),
|
|
.phy_tx_rst(qsfp0_tx_rst_4_int),
|
|
.phy_xgmii_txd(qsfp0_txd_4_int),
|
|
.phy_xgmii_txc(qsfp0_txc_4_int),
|
|
.phy_rx_clk(qsfp0_rx_clk_4_int),
|
|
.phy_rx_rst(qsfp0_rx_rst_4_int),
|
|
.phy_xgmii_rxd(qsfp0_rxd_4_int),
|
|
.phy_xgmii_rxc(qsfp0_rxc_4_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
// QSFP1
|
|
assign qsfp1_modsell = 1'b0;
|
|
assign qsfp1_resetl = 1'b1;
|
|
assign qsfp1_lpmode = 1'b0;
|
|
assign qsfp1_refclk_reset = qsfp_refclk_reset_reg;
|
|
assign qsfp1_fs = 2'b10;
|
|
|
|
wire qsfp1_tx_clk_1_int;
|
|
wire qsfp1_tx_rst_1_int;
|
|
wire [63:0] qsfp1_txd_1_int;
|
|
wire [7:0] qsfp1_txc_1_int;
|
|
wire qsfp1_rx_clk_1_int;
|
|
wire qsfp1_rx_rst_1_int;
|
|
wire [63:0] qsfp1_rxd_1_int;
|
|
wire [7:0] qsfp1_rxc_1_int;
|
|
wire qsfp1_tx_clk_2_int;
|
|
wire qsfp1_tx_rst_2_int;
|
|
wire [63:0] qsfp1_txd_2_int;
|
|
wire [7:0] qsfp1_txc_2_int;
|
|
wire qsfp1_rx_clk_2_int;
|
|
wire qsfp1_rx_rst_2_int;
|
|
wire [63:0] qsfp1_rxd_2_int;
|
|
wire [7:0] qsfp1_rxc_2_int;
|
|
wire qsfp1_tx_clk_3_int;
|
|
wire qsfp1_tx_rst_3_int;
|
|
wire [63:0] qsfp1_txd_3_int;
|
|
wire [7:0] qsfp1_txc_3_int;
|
|
wire qsfp1_rx_clk_3_int;
|
|
wire qsfp1_rx_rst_3_int;
|
|
wire [63:0] qsfp1_rxd_3_int;
|
|
wire [7:0] qsfp1_rxc_3_int;
|
|
wire qsfp1_tx_clk_4_int;
|
|
wire qsfp1_tx_rst_4_int;
|
|
wire [63:0] qsfp1_txd_4_int;
|
|
wire [7:0] qsfp1_txc_4_int;
|
|
wire qsfp1_rx_clk_4_int;
|
|
wire qsfp1_rx_rst_4_int;
|
|
wire [63:0] qsfp1_rxd_4_int;
|
|
wire [7:0] qsfp1_rxc_4_int;
|
|
|
|
wire qsfp1_rx_block_lock_1;
|
|
wire qsfp1_rx_block_lock_2;
|
|
wire qsfp1_rx_block_lock_3;
|
|
wire qsfp1_rx_block_lock_4;
|
|
|
|
wire qsfp1_mgt_refclk_1;
|
|
|
|
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst (
|
|
.I (qsfp1_mgt_refclk_1_p),
|
|
.IB (qsfp1_mgt_refclk_1_n),
|
|
.CEB (1'b0),
|
|
.O (qsfp1_mgt_refclk_1),
|
|
.ODIV2 ()
|
|
);
|
|
|
|
wire qsfp1_qpll0lock;
|
|
wire qsfp1_qpll0outclk;
|
|
wire qsfp1_qpll0outrefclk;
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(1)
|
|
)
|
|
qsfp1_phy_1_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
|
|
.xcvr_qpll0lock_out(qsfp1_qpll0lock),
|
|
.xcvr_qpll0outclk_out(qsfp1_qpll0outclk),
|
|
.xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(1'b0),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(1'b0),
|
|
.xcvr_qpll0refclk_in(1'b0),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp1_tx1_p),
|
|
.xcvr_txn(qsfp1_tx1_n),
|
|
.xcvr_rxp(qsfp1_rx1_p),
|
|
.xcvr_rxn(qsfp1_rx1_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp1_tx_clk_1_int),
|
|
.phy_tx_rst(qsfp1_tx_rst_1_int),
|
|
.phy_xgmii_txd(qsfp1_txd_1_int),
|
|
.phy_xgmii_txc(qsfp1_txc_1_int),
|
|
.phy_rx_clk(qsfp1_rx_clk_1_int),
|
|
.phy_rx_rst(qsfp1_rx_rst_1_int),
|
|
.phy_xgmii_rxd(qsfp1_rxd_1_int),
|
|
.phy_xgmii_rxc(qsfp1_rxc_1_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0)
|
|
)
|
|
qsfp1_phy_2_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp1_tx2_p),
|
|
.xcvr_txn(qsfp1_tx2_n),
|
|
.xcvr_rxp(qsfp1_rx2_p),
|
|
.xcvr_rxn(qsfp1_rx2_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp1_tx_clk_2_int),
|
|
.phy_tx_rst(qsfp1_tx_rst_2_int),
|
|
.phy_xgmii_txd(qsfp1_txd_2_int),
|
|
.phy_xgmii_txc(qsfp1_txc_2_int),
|
|
.phy_rx_clk(qsfp1_rx_clk_2_int),
|
|
.phy_rx_rst(qsfp1_rx_rst_2_int),
|
|
.phy_xgmii_rxd(qsfp1_rxd_2_int),
|
|
.phy_xgmii_rxc(qsfp1_rxc_2_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0)
|
|
)
|
|
qsfp1_phy_3_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp1_tx3_p),
|
|
.xcvr_txn(qsfp1_tx3_n),
|
|
.xcvr_rxp(qsfp1_rx3_p),
|
|
.xcvr_rxn(qsfp1_rx3_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp1_tx_clk_3_int),
|
|
.phy_tx_rst(qsfp1_tx_rst_3_int),
|
|
.phy_xgmii_txd(qsfp1_txd_3_int),
|
|
.phy_xgmii_txc(qsfp1_txc_3_int),
|
|
.phy_rx_clk(qsfp1_rx_clk_3_int),
|
|
.phy_rx_rst(qsfp1_rx_rst_3_int),
|
|
.phy_xgmii_rxd(qsfp1_rxd_3_int),
|
|
.phy_xgmii_rxc(qsfp1_rxc_3_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
eth_xcvr_phy_wrapper #(
|
|
.HAS_COMMON(0)
|
|
)
|
|
qsfp1_phy_4_inst (
|
|
.xcvr_ctrl_clk(clk_125mhz_int),
|
|
.xcvr_ctrl_rst(rst_125mhz_int),
|
|
|
|
// Common
|
|
.xcvr_gtpowergood_out(),
|
|
|
|
// PLL out
|
|
.xcvr_gtrefclk00_in(1'b0),
|
|
.xcvr_qpll0lock_out(),
|
|
.xcvr_qpll0outclk_out(),
|
|
.xcvr_qpll0outrefclk_out(),
|
|
|
|
// PLL in
|
|
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
|
|
.xcvr_qpll0reset_out(),
|
|
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
|
|
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
|
|
|
|
// Serial data
|
|
.xcvr_txp(qsfp1_tx4_p),
|
|
.xcvr_txn(qsfp1_tx4_n),
|
|
.xcvr_rxp(qsfp1_rx4_p),
|
|
.xcvr_rxn(qsfp1_rx4_n),
|
|
|
|
// PHY connections
|
|
.phy_tx_clk(qsfp1_tx_clk_4_int),
|
|
.phy_tx_rst(qsfp1_tx_rst_4_int),
|
|
.phy_xgmii_txd(qsfp1_txd_4_int),
|
|
.phy_xgmii_txc(qsfp1_txc_4_int),
|
|
.phy_rx_clk(qsfp1_rx_clk_4_int),
|
|
.phy_rx_rst(qsfp1_rx_rst_4_int),
|
|
.phy_xgmii_rxd(qsfp1_rxd_4_int),
|
|
.phy_xgmii_rxc(qsfp1_rxc_4_int),
|
|
.phy_tx_bad_block(),
|
|
.phy_rx_error_count(),
|
|
.phy_rx_bad_block(),
|
|
.phy_rx_sequence_error(),
|
|
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
|
|
.phy_rx_high_ber(),
|
|
.phy_tx_prbs31_enable(),
|
|
.phy_rx_prbs31_enable()
|
|
);
|
|
|
|
fpga_core
|
|
core_inst (
|
|
/*
|
|
* Clock: 156.25 MHz
|
|
* Synchronous reset
|
|
*/
|
|
.clk(clk_156mhz_int),
|
|
.rst(rst_156mhz_int),
|
|
/*
|
|
* GPIO
|
|
*/
|
|
.sw(sw_int),
|
|
.led(led),
|
|
/*
|
|
* Ethernet: QSFP28
|
|
*/
|
|
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
|
|
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
|
|
.qsfp0_txd_1(qsfp0_txd_1_int),
|
|
.qsfp0_txc_1(qsfp0_txc_1_int),
|
|
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
|
|
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
|
|
.qsfp0_rxd_1(qsfp0_rxd_1_int),
|
|
.qsfp0_rxc_1(qsfp0_rxc_1_int),
|
|
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
|
|
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
|
|
.qsfp0_txd_2(qsfp0_txd_2_int),
|
|
.qsfp0_txc_2(qsfp0_txc_2_int),
|
|
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
|
|
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
|
|
.qsfp0_rxd_2(qsfp0_rxd_2_int),
|
|
.qsfp0_rxc_2(qsfp0_rxc_2_int),
|
|
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
|
|
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
|
|
.qsfp0_txd_3(qsfp0_txd_3_int),
|
|
.qsfp0_txc_3(qsfp0_txc_3_int),
|
|
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
|
|
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
|
|
.qsfp0_rxd_3(qsfp0_rxd_3_int),
|
|
.qsfp0_rxc_3(qsfp0_rxc_3_int),
|
|
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
|
|
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
|
|
.qsfp0_txd_4(qsfp0_txd_4_int),
|
|
.qsfp0_txc_4(qsfp0_txc_4_int),
|
|
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
|
|
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
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.qsfp0_rxd_4(qsfp0_rxd_4_int),
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.qsfp0_rxc_4(qsfp0_rxc_4_int),
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.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
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.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
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.qsfp1_txd_1(qsfp1_txd_1_int),
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.qsfp1_txc_1(qsfp1_txc_1_int),
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.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
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.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
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.qsfp1_rxd_1(qsfp1_rxd_1_int),
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.qsfp1_rxc_1(qsfp1_rxc_1_int),
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.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
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.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
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.qsfp1_txd_2(qsfp1_txd_2_int),
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|
.qsfp1_txc_2(qsfp1_txc_2_int),
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|
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
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|
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
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|
.qsfp1_rxd_2(qsfp1_rxd_2_int),
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|
.qsfp1_rxc_2(qsfp1_rxc_2_int),
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|
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
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|
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
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|
.qsfp1_txd_3(qsfp1_txd_3_int),
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|
.qsfp1_txc_3(qsfp1_txc_3_int),
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|
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
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|
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
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|
.qsfp1_rxd_3(qsfp1_rxd_3_int),
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|
.qsfp1_rxc_3(qsfp1_rxc_3_int),
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|
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
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|
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
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|
.qsfp1_txd_4(qsfp1_txd_4_int),
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|
.qsfp1_txc_4(qsfp1_txc_4_int),
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|
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
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|
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
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|
.qsfp1_rxd_4(qsfp1_rxd_4_int),
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|
.qsfp1_rxc_4(qsfp1_rxc_4_int),
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|
/*
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* UART: 115200 bps, 8N1
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*/
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.uart_rxd(uart_rxd),
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|
.uart_txd(uart_txd_int)
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|
);
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|
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endmodule
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`resetall
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