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corundum
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corundum
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fpga
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mqnic
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VCU118
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fpga_25g
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Alex Forencich
218f2e2bb3
25G designs use double width sync datapath by default
...
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-18 23:31:36 -07:00
..
common
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00
debounce_switch.v
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00
fpga_core.v
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
fpga.v
Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
2022-07-08 22:07:18 -07:00
sync_signal.v
Unified 10G/25G design for VCU118
2022-03-14 21:40:29 -07:00
