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176 lines
6.2 KiB
Verilog
176 lines
6.2 KiB
Verilog
/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Ultrascale PCIe configuration shim
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*/
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module pcie_us_cfg #
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(
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parameter PF_COUNT = 1,
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parameter VF_COUNT = 0,
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parameter VF_OFFSET = 64,
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parameter F_COUNT = PF_COUNT+VF_COUNT,
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parameter READ_EXT_TAG_ENABLE = 1,
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parameter READ_MAX_READ_REQ_SIZE = 1,
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parameter READ_MAX_PAYLOAD_SIZE = 1,
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parameter PCIE_CAP_OFFSET = 12'h0C0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Configuration outputs
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*/
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output wire [F_COUNT-1:0] ext_tag_enable,
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output wire [F_COUNT*3-1:0] max_read_request_size,
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output wire [F_COUNT*3-1:0] max_payload_size,
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/*
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* Interface to Ultrascale PCIe IP core
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*/
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output wire [9:0] cfg_mgmt_addr,
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output wire [7:0] cfg_mgmt_function_number,
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output wire cfg_mgmt_write,
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output wire [31:0] cfg_mgmt_write_data,
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output wire [3:0] cfg_mgmt_byte_enable,
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output wire cfg_mgmt_read,
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input wire [31:0] cfg_mgmt_read_data,
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input wire cfg_mgmt_read_write_done
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);
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localparam READ_REV_CTRL = READ_EXT_TAG_ENABLE || READ_MAX_READ_REQ_SIZE || READ_MAX_PAYLOAD_SIZE;
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localparam DEV_CTRL_OFFSET = PCIE_CAP_OFFSET + 12'h008;
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reg [F_COUNT-1:0] ext_tag_enable_reg = {F_COUNT{1'b0}}, ext_tag_enable_next;
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reg [F_COUNT*3-1:0] max_read_request_size_reg = {F_COUNT{3'd0}}, max_read_request_size_next;
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reg [F_COUNT*3-1:0] max_payload_size_reg = {F_COUNT{3'd0}}, max_payload_size_next;
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reg [9:0] cfg_mgmt_addr_reg = 10'd0, cfg_mgmt_addr_next;
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reg [7:0] cfg_mgmt_function_number_reg = 8'd0, cfg_mgmt_function_number_next;
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reg cfg_mgmt_write_reg = 1'b0, cfg_mgmt_write_next;
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reg [31:0] cfg_mgmt_write_data_reg = 32'd0, cfg_mgmt_write_data_next;
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reg [3:0] cfg_mgmt_byte_enable_reg = 4'd0, cfg_mgmt_byte_enable_next;
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reg cfg_mgmt_read_reg = 1'b0, cfg_mgmt_read_next;
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reg [7:0] delay_reg = 8'hff, delay_next;
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reg [7:0] func_cnt_reg = 8'd0, func_cnt_next;
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assign ext_tag_enable = ext_tag_enable_reg;
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assign max_read_request_size = max_read_request_size_reg;
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assign max_payload_size = max_payload_size_reg;
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assign cfg_mgmt_addr = cfg_mgmt_addr_reg;
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assign cfg_mgmt_function_number = cfg_mgmt_function_number_reg;
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assign cfg_mgmt_write = cfg_mgmt_write_reg;
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assign cfg_mgmt_write_data = cfg_mgmt_write_data_reg;
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assign cfg_mgmt_byte_enable = cfg_mgmt_byte_enable_reg;
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assign cfg_mgmt_read = cfg_mgmt_read_reg;
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always @* begin
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ext_tag_enable_next = ext_tag_enable_reg;
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max_read_request_size_next = max_read_request_size_reg;
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max_payload_size_next = max_payload_size_reg;
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cfg_mgmt_addr_next = cfg_mgmt_addr_reg;
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cfg_mgmt_function_number_next = cfg_mgmt_function_number_reg;
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cfg_mgmt_write_next = cfg_mgmt_write_reg && !cfg_mgmt_read_write_done;
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cfg_mgmt_write_data_next = cfg_mgmt_write_data_reg;
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cfg_mgmt_byte_enable_next = cfg_mgmt_byte_enable_reg;
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cfg_mgmt_read_next = cfg_mgmt_read_reg && !cfg_mgmt_read_write_done;
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delay_next = delay_reg;
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func_cnt_next = func_cnt_reg;
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if (delay_reg > 0) begin
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delay_next = delay_reg - 1;
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end else begin
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cfg_mgmt_addr_next = DEV_CTRL_OFFSET >> 2;
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cfg_mgmt_read_next = 1'b1;
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if (cfg_mgmt_read_write_done) begin
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cfg_mgmt_read_next = 1'b0;
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ext_tag_enable_next[func_cnt_reg] = cfg_mgmt_read_data[8];
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max_read_request_size_next[func_cnt_reg*3 +: 3] = cfg_mgmt_read_data[14:12];
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max_payload_size_next[func_cnt_reg*3 +: 3] = cfg_mgmt_read_data[7:5];
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if (func_cnt_reg == F_COUNT-1) begin
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func_cnt_next = 0;
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cfg_mgmt_function_number_next = 0;
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end else if (func_cnt_reg == PF_COUNT-1) begin
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func_cnt_next = func_cnt_reg + 1;
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cfg_mgmt_function_number_next = VF_OFFSET;
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end else begin
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func_cnt_next = func_cnt_reg + 1;
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cfg_mgmt_function_number_next = cfg_mgmt_function_number_reg + 1;
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end
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delay_next = 8'hff;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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ext_tag_enable_reg <= {F_COUNT{1'b0}};
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max_read_request_size_reg <= {F_COUNT{3'd0}};
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max_payload_size_reg <= {F_COUNT{3'd0}};
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cfg_mgmt_addr_reg <= 10'd0;
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cfg_mgmt_function_number_reg <= 8'd0;
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cfg_mgmt_write_reg <= 1'b0;
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cfg_mgmt_read_reg <= 1'b0;
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delay_reg <= 8'hff;
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func_cnt_reg <= 8'd0;
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end else begin
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ext_tag_enable_reg <= ext_tag_enable_next;
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max_read_request_size_reg <= max_read_request_size_next;
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max_payload_size_reg <= max_payload_size_next;
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cfg_mgmt_addr_reg <= cfg_mgmt_addr_next;
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cfg_mgmt_function_number_reg <= cfg_mgmt_function_number_next;
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cfg_mgmt_write_reg <= cfg_mgmt_write_next;
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cfg_mgmt_read_reg <= cfg_mgmt_read_next;
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delay_reg <= delay_next;
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func_cnt_reg <= func_cnt_next;
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end
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cfg_mgmt_write_data_reg <= cfg_mgmt_write_data_next;
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cfg_mgmt_byte_enable_reg <= cfg_mgmt_byte_enable_next;
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end
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endmodule
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`resetall
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