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271 lines
9.8 KiB
Verilog
271 lines
9.8 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 RAM read interface
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*/
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module axi_ram_rd_if #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 16,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Width of ID signal
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parameter ID_WIDTH = 8,
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// Propagate aruser signal
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parameter ARUSER_ENABLE = 0,
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// Width of aruser signal
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parameter ARUSER_WIDTH = 1,
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// Propagate ruser signal
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parameter RUSER_ENABLE = 0,
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// Width of ruser signal
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parameter RUSER_WIDTH = 1,
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// Extra pipeline register on output
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parameter PIPELINE_OUTPUT = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [ID_WIDTH-1:0] s_axi_arid,
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input wire [ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [7:0] s_axi_arlen,
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input wire [2:0] s_axi_arsize,
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input wire [1:0] s_axi_arburst,
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input wire s_axi_arlock,
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input wire [3:0] s_axi_arcache,
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input wire [2:0] s_axi_arprot,
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input wire [3:0] s_axi_arqos,
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input wire [3:0] s_axi_arregion,
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input wire [ARUSER_WIDTH-1:0] s_axi_aruser,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [ID_WIDTH-1:0] s_axi_rid,
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output wire [DATA_WIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rlast,
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output wire [RUSER_WIDTH-1:0] s_axi_ruser,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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/*
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* RAM interface
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*/
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output wire [ID_WIDTH-1:0] ram_rd_cmd_id,
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output wire [ADDR_WIDTH-1:0] ram_rd_cmd_addr,
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output wire ram_rd_cmd_lock,
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output wire [3:0] ram_rd_cmd_cache,
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output wire [2:0] ram_rd_cmd_prot,
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output wire [3:0] ram_rd_cmd_qos,
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output wire [3:0] ram_rd_cmd_region,
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output wire [ARUSER_WIDTH-1:0] ram_rd_cmd_auser,
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output wire ram_rd_cmd_en,
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output wire ram_rd_cmd_last,
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input wire ram_rd_cmd_ready,
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input wire [ID_WIDTH-1:0] ram_rd_resp_id,
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input wire [DATA_WIDTH-1:0] ram_rd_resp_data,
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input wire ram_rd_resp_last,
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input wire [RUSER_WIDTH-1:0] ram_rd_resp_user,
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input wire ram_rd_resp_valid,
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output wire ram_rd_resp_ready
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);
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parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
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parameter WORD_WIDTH = STRB_WIDTH;
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parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
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// bus width assertions
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initial begin
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if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
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$error("Error: AXI data width not evenly divisble (instance %m)");
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$finish;
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end
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if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
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$error("Error: AXI word width must be even power of two (instance %m)");
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$finish;
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end
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end
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localparam [0:0]
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STATE_IDLE = 1'd0,
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STATE_BURST = 1'd1;
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reg [0:0] state_reg = STATE_IDLE, state_next;
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reg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next;
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reg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next;
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reg read_lock_reg = 1'b0, read_lock_next;
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reg [3:0] read_cache_reg = 4'd0, read_cache_next;
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reg [2:0] read_prot_reg = 3'd0, read_prot_next;
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reg [3:0] read_qos_reg = 4'd0, read_qos_next;
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reg [3:0] read_region_reg = 4'd0, read_region_next;
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reg [ARUSER_WIDTH-1:0] read_aruser_reg = {ARUSER_WIDTH{1'b0}}, read_aruser_next;
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reg read_addr_valid_reg = 1'b0, read_addr_valid_next;
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reg read_last_reg = 1'b0, read_last_next;
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reg [7:0] read_count_reg = 8'd0, read_count_next;
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reg [2:0] read_size_reg = 3'd0, read_size_next;
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reg [1:0] read_burst_reg = 2'd0, read_burst_next;
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reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
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reg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}};
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reg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
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reg s_axi_rlast_pipe_reg = 1'b0;
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reg [RUSER_WIDTH-1:0] s_axi_ruser_pipe_reg = {RUSER_WIDTH{1'b0}};
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reg s_axi_rvalid_pipe_reg = 1'b0;
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assign s_axi_arready = s_axi_arready_reg;
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assign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : ram_rd_resp_id;
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assign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : ram_rd_resp_data;
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assign s_axi_rresp = 2'b00;
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assign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : ram_rd_resp_last;
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assign s_axi_ruser = PIPELINE_OUTPUT ? s_axi_ruser_pipe_reg : ram_rd_resp_user;
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assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : ram_rd_resp_valid;
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assign ram_rd_cmd_id = read_id_reg;
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assign ram_rd_cmd_addr = read_addr_reg;
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assign ram_rd_cmd_lock = read_lock_reg;
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assign ram_rd_cmd_cache = read_cache_reg;
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assign ram_rd_cmd_prot = read_prot_reg;
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assign ram_rd_cmd_qos = read_qos_reg;
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assign ram_rd_cmd_region = read_region_reg;
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assign ram_rd_cmd_auser = ARUSER_ENABLE ? read_aruser_reg : {ARUSER_WIDTH{1'b0}};
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assign ram_rd_cmd_en = read_addr_valid_reg;
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assign ram_rd_cmd_last = read_last_reg;
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assign ram_rd_resp_ready = s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg);
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always @* begin
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state_next = STATE_IDLE;
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read_id_next = read_id_reg;
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read_addr_next = read_addr_reg;
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read_lock_next = read_lock_reg;
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read_cache_next = read_cache_reg;
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read_prot_next = read_prot_reg;
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read_qos_next = read_qos_reg;
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read_region_next = read_region_reg;
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read_aruser_next = read_aruser_reg;
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read_addr_valid_next = read_addr_valid_reg && !ram_rd_cmd_ready;
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read_last_next = read_last_reg;
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read_count_next = read_count_reg;
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read_size_next = read_size_reg;
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read_burst_next = read_burst_reg;
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s_axi_arready_next = 1'b0;
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case (state_reg)
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STATE_IDLE: begin
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s_axi_arready_next = 1'b1;
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if (s_axi_arready && s_axi_arvalid) begin
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read_id_next = s_axi_arid;
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read_addr_next = s_axi_araddr;
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read_lock_next = s_axi_arlock;
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read_cache_next = s_axi_arcache;
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read_prot_next = s_axi_arprot;
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read_qos_next = s_axi_arqos;
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read_region_next = s_axi_arregion;
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read_aruser_next = s_axi_aruser;
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read_count_next = s_axi_arlen;
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read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
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read_burst_next = s_axi_arburst;
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s_axi_arready_next = 1'b0;
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read_last_next = read_count_next == 0;
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read_addr_valid_next = 1'b1;
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state_next = STATE_BURST;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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STATE_BURST: begin
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if (ram_rd_cmd_ready && ram_rd_cmd_en) begin
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if (read_burst_reg != 2'b00) begin
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read_addr_next = read_addr_reg + (1 << read_size_reg);
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end
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read_count_next = read_count_reg - 1;
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read_last_next = read_count_next == 0;
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if (read_count_reg > 0) begin
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read_addr_valid_next = 1'b1;
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state_next = STATE_BURST;
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end else begin
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s_axi_arready_next = 1'b1;
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state_next = STATE_IDLE;
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end
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end else begin
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state_next = STATE_BURST;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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state_reg <= STATE_IDLE;
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read_addr_valid_reg <= 1'b0;
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s_axi_arready_reg <= 1'b0;
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s_axi_rvalid_pipe_reg <= 1'b0;
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end else begin
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state_reg <= state_next;
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read_addr_valid_reg <= read_addr_valid_next;
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s_axi_arready_reg <= s_axi_arready_next;
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if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
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s_axi_rvalid_pipe_reg <= ram_rd_resp_valid;
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end
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end
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read_id_reg <= read_id_next;
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read_addr_reg <= read_addr_next;
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read_lock_reg <= read_lock_next;
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read_cache_reg <= read_cache_next;
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read_prot_reg <= read_prot_next;
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read_qos_reg <= read_qos_next;
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read_region_reg <= read_region_next;
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read_aruser_reg <= read_aruser_next;
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read_last_reg <= read_last_next;
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read_count_reg <= read_count_next;
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read_size_reg <= read_size_next;
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read_burst_reg <= read_burst_next;
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if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
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s_axi_rid_pipe_reg <= ram_rd_resp_id;
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s_axi_rdata_pipe_reg <= ram_rd_resp_data;
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s_axi_rlast_pipe_reg <= ram_rd_resp_last;
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s_axi_ruser_pipe_reg <= ram_rd_resp_user;
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end
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end
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endmodule
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