Alex Forencich 2714ba5cdd merged changes in pcie

2022-10-12 23:57:47 -07:00

..

app

fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section

2022-10-12 17:12:23 -07:00

common

fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section

2022-10-12 17:12:23 -07:00

lib

merged changes in pcie

2022-10-12 23:57:47 -07:00

mqnic

fpga/mqnic: Disable MIGs by default

2022-10-12 23:57:27 -07:00

build_images_project.ini

Rework build_images settings

2022-07-13 01:18:42 -07:00

build_images.py

fpga/build_images.py: update quartus message parsing

2022-08-04 13:40:34 -07:00

collect_utilization.py

Add build automation scripts

2022-03-02 23:20:59 -08:00

watch.sh

Change interval

2022-07-13 01:18:55 -07:00