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corundum/example/Arty/fpga/rtl
History
Alex Forencich 27ed447005 Use common sync_reset module files
2020-03-27 18:27:45 -07:00
..
debounce_switch.v
Add Arty example design
2019-03-28 19:38:55 -07:00
fpga_core.v
Fix typo
2019-07-19 10:29:55 -07:00
fpga.v
Use common sync_reset module files
2020-03-27 18:27:45 -07:00
sync_signal.v
Add Arty example design
2019-03-28 19:38:55 -07:00