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511 lines
17 KiB
Verilog
511 lines
17 KiB
Verilog
/*
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Copyright (c) 2016-2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream consistent overhead byte stuffing (COBS) encoder
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*/
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module axis_cobs_encode #
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(
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// append zero for in band framing
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parameter APPEND_ZERO = 1
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [7:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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input wire s_axis_tlast,
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input wire s_axis_tuser,
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/*
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* AXI output
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*/
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output wire [7:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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output wire m_axis_tlast,
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output wire m_axis_tuser
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);
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// state register
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localparam [1:0]
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INPUT_STATE_IDLE = 2'd0,
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INPUT_STATE_SEGMENT = 2'd1,
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INPUT_STATE_FINAL_ZERO = 2'd2,
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INPUT_STATE_APPEND_ZERO = 2'd3;
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reg [1:0] input_state_reg = INPUT_STATE_IDLE, input_state_next;
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localparam [0:0]
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OUTPUT_STATE_IDLE = 1'd0,
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OUTPUT_STATE_SEGMENT = 1'd1;
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reg [0:0] output_state_reg = OUTPUT_STATE_IDLE, output_state_next;
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reg [7:0] input_count_reg = 8'd0, input_count_next;
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reg [7:0] output_count_reg = 8'd0, output_count_next;
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reg fail_frame_reg = 1'b0, fail_frame_next;
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// internal datapath
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reg [7:0] m_axis_tdata_int;
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reg m_axis_tvalid_int;
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reg m_axis_tready_int_reg = 1'b0;
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reg m_axis_tlast_int;
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reg m_axis_tuser_int;
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wire m_axis_tready_int_early;
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reg s_axis_tready_mask;
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reg [7:0] code_fifo_in_tdata;
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reg code_fifo_in_tvalid;
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reg code_fifo_in_tlast;
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reg code_fifo_in_tuser;
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wire code_fifo_in_tready;
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wire [7:0] code_fifo_out_tdata;
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wire code_fifo_out_tvalid;
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wire code_fifo_out_tlast;
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wire code_fifo_out_tuser;
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reg code_fifo_out_tready;
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reg [7:0] data_fifo_in_tdata;
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reg data_fifo_in_tvalid;
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reg data_fifo_in_tlast;
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wire data_fifo_in_tready;
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wire [7:0] data_fifo_out_tdata;
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wire data_fifo_out_tvalid;
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wire data_fifo_out_tlast;
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reg data_fifo_out_tready;
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assign s_axis_tready = code_fifo_in_tready && data_fifo_in_tready && s_axis_tready_mask;
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axis_fifo #(
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.DEPTH(256),
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.DATA_WIDTH(8),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(1),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(1),
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.USER_WIDTH(1),
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.FRAME_FIFO(0)
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)
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code_fifo_inst (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(code_fifo_in_tdata),
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.s_axis_tkeep(0),
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.s_axis_tvalid(code_fifo_in_tvalid),
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.s_axis_tready(code_fifo_in_tready),
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.s_axis_tlast(code_fifo_in_tlast),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(code_fifo_in_tuser),
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// AXI output
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.m_axis_tdata(code_fifo_out_tdata),
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.m_axis_tkeep(),
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.m_axis_tvalid(code_fifo_out_tvalid),
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.m_axis_tready(code_fifo_out_tready),
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.m_axis_tlast(code_fifo_out_tlast),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(code_fifo_out_tuser),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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axis_fifo #(
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.DEPTH(256),
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.DATA_WIDTH(8),
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.KEEP_ENABLE(0),
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.LAST_ENABLE(1),
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.ID_ENABLE(0),
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.DEST_ENABLE(0),
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.USER_ENABLE(0),
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.FRAME_FIFO(0)
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)
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data_fifo_inst (
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.clk(clk),
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.rst(rst),
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// AXI input
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.s_axis_tdata(data_fifo_in_tdata),
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.s_axis_tkeep(0),
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.s_axis_tvalid(data_fifo_in_tvalid),
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.s_axis_tready(data_fifo_in_tready),
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.s_axis_tlast(data_fifo_in_tlast),
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.s_axis_tid(0),
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.s_axis_tdest(0),
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.s_axis_tuser(0),
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// AXI output
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.m_axis_tdata(data_fifo_out_tdata),
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.m_axis_tkeep(),
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.m_axis_tvalid(data_fifo_out_tvalid),
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.m_axis_tready(data_fifo_out_tready),
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.m_axis_tlast(data_fifo_out_tlast),
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.m_axis_tid(),
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.m_axis_tdest(),
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.m_axis_tuser(),
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// Status
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.status_overflow(),
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.status_bad_frame(),
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.status_good_frame()
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);
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always @* begin
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input_state_next = INPUT_STATE_IDLE;
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input_count_next = input_count_reg;
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fail_frame_next = fail_frame_reg;
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s_axis_tready_mask = 1'b0;
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code_fifo_in_tdata = 8'd0;
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code_fifo_in_tvalid = 1'b0;
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code_fifo_in_tlast = 1'b0;
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code_fifo_in_tuser = 1'b0;
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data_fifo_in_tdata = s_axis_tdata;
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data_fifo_in_tvalid = 1'b0;
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data_fifo_in_tlast = 1'b0;
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case (input_state_reg)
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INPUT_STATE_IDLE: begin
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// idle state
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s_axis_tready_mask = 1'b1;
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fail_frame_next = 1'b0;
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if (s_axis_tready && s_axis_tvalid) begin
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// valid input data
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if (s_axis_tdata == 8'd0 || (s_axis_tlast && s_axis_tuser)) begin
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// got a zero or propagated error, so store a zero code
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code_fifo_in_tdata = 8'd1;
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code_fifo_in_tvalid = 1'b1;
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if (s_axis_tlast) begin
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// last byte, so close out the frame
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fail_frame_next = s_axis_tuser;
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input_state_next = INPUT_STATE_FINAL_ZERO;
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end else begin
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// return to idle to await next segment
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input_state_next = INPUT_STATE_IDLE;
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end
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end else begin
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// got something other than a zero, so store it and init the segment counter
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input_count_next = 8'd2;
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data_fifo_in_tdata = s_axis_tdata;
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data_fifo_in_tvalid = 1'b1;
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if (s_axis_tlast) begin
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// last byte, so store the code and close out the frame
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code_fifo_in_tdata = 8'd2;
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code_fifo_in_tvalid = 1'b1;
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if (APPEND_ZERO) begin
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// zero frame mode, need to add a zero code to end the frame
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input_state_next = INPUT_STATE_APPEND_ZERO;
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end else begin
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// normal frame mode, close out the frame
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data_fifo_in_tlast = 1'b1;
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input_state_next = INPUT_STATE_IDLE;
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end
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end else begin
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// await more segment data
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input_state_next = INPUT_STATE_SEGMENT;
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end
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end
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end else begin
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input_state_next = INPUT_STATE_IDLE;
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end
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end
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INPUT_STATE_SEGMENT: begin
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// encode segment
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s_axis_tready_mask = 1'b1;
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fail_frame_next = 1'b0;
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if (s_axis_tready && s_axis_tvalid) begin
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// valid input data
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if (s_axis_tdata == 8'd0 || (s_axis_tlast && s_axis_tuser)) begin
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// got a zero or propagated error, so store the code
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code_fifo_in_tdata = input_count_reg;
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code_fifo_in_tvalid = 1'b1;
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if (s_axis_tlast) begin
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// last byte, so close out the frame
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fail_frame_next = s_axis_tuser;
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input_state_next = INPUT_STATE_FINAL_ZERO;
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end else begin
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// return to idle to await next segment
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input_state_next = INPUT_STATE_IDLE;
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end
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end else begin
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// got something other than a zero, so store it and increment the segment counter
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input_count_next = input_count_reg+1;
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data_fifo_in_tdata = s_axis_tdata;
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data_fifo_in_tvalid = 1'b1;
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if (input_count_reg == 8'd254) begin
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// 254 bytes in frame, so dump and reset counter
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code_fifo_in_tdata = input_count_reg+1;
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code_fifo_in_tvalid = 1'b1;
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input_count_next = 8'd1;
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end
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if (s_axis_tlast) begin
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// last byte, so store the code and close out the frame
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code_fifo_in_tdata = input_count_reg+1;
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code_fifo_in_tvalid = 1'b1;
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if (APPEND_ZERO) begin
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// zero frame mode, need to add a zero code to end the frame
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input_state_next = INPUT_STATE_APPEND_ZERO;
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end else begin
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// normal frame mode, close out the frame
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data_fifo_in_tlast = 1'b1;
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input_state_next = INPUT_STATE_IDLE;
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end
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end else begin
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// await more segment data
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input_state_next = INPUT_STATE_SEGMENT;
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end
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end
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end else begin
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input_state_next = INPUT_STATE_SEGMENT;
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end
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end
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INPUT_STATE_FINAL_ZERO: begin
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// final zero code required
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s_axis_tready_mask = 1'b0;
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if (code_fifo_in_tready) begin
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// push a zero code and close out frame
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if (fail_frame_reg) begin
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code_fifo_in_tdata = 8'd2;
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code_fifo_in_tuser = 1'b1;
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end else begin
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code_fifo_in_tdata = 8'd1;
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end
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code_fifo_in_tvalid = 1'b1;
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if (APPEND_ZERO) begin
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// zero frame mode, need to add a zero code to end the frame
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input_state_next = INPUT_STATE_APPEND_ZERO;
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end else begin
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// normal frame mode, close out the frame
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code_fifo_in_tlast = 1'b1;
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fail_frame_next = 1'b0;
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input_state_next = INPUT_STATE_IDLE;
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end
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end else begin
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input_state_next = INPUT_STATE_FINAL_ZERO;
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end
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end
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INPUT_STATE_APPEND_ZERO: begin
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// append zero for zero framing
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s_axis_tready_mask = 1'b0;
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if (code_fifo_in_tready) begin
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// push frame termination code and close out frame
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code_fifo_in_tdata = 8'd0;
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code_fifo_in_tlast = 1'b1;
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code_fifo_in_tuser = fail_frame_reg;
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code_fifo_in_tvalid = 1'b1;
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fail_frame_next = 1'b0;
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input_state_next = INPUT_STATE_IDLE;
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end else begin
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input_state_next = INPUT_STATE_APPEND_ZERO;
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end
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end
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endcase
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end
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always @* begin
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output_state_next = OUTPUT_STATE_IDLE;
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output_count_next = output_count_reg;
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m_axis_tdata_int = 8'd0;
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m_axis_tvalid_int = 1'b0;
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m_axis_tlast_int = 1'b0;
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m_axis_tuser_int = 1'b0;
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code_fifo_out_tready = 1'b0;
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data_fifo_out_tready = 1'b0;
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case (output_state_reg)
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OUTPUT_STATE_IDLE: begin
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// idle state
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if (m_axis_tready_int_reg && code_fifo_out_tvalid) begin
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// transfer out code byte and load counter
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m_axis_tdata_int = code_fifo_out_tdata;
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m_axis_tlast_int = code_fifo_out_tlast;
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m_axis_tuser_int = code_fifo_out_tuser && code_fifo_out_tlast;
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output_count_next = code_fifo_out_tdata-1;
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m_axis_tvalid_int = 1'b1;
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code_fifo_out_tready = 1'b1;
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if (code_fifo_out_tdata == 8'd0 || code_fifo_out_tdata == 8'd1 || code_fifo_out_tuser) begin
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// frame termination and zero codes will be followed by codes
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output_state_next = OUTPUT_STATE_IDLE;
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end else begin
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// transfer out data
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output_state_next = OUTPUT_STATE_SEGMENT;
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end
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end else begin
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output_state_next = OUTPUT_STATE_IDLE;
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end
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end
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OUTPUT_STATE_SEGMENT: begin
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// segment output
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if (m_axis_tready_int_reg && data_fifo_out_tvalid) begin
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// transfer out data byte and decrement counter
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m_axis_tdata_int = data_fifo_out_tdata;
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m_axis_tlast_int = data_fifo_out_tlast;
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output_count_next = output_count_reg - 1;
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m_axis_tvalid_int = 1'b1;
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data_fifo_out_tready = 1'b1;
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if (output_count_reg == 1'b1) begin
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// done with segment, get a code byte next
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output_state_next = OUTPUT_STATE_IDLE;
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end else begin
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// more data to transfer
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output_state_next = OUTPUT_STATE_SEGMENT;
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end
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end else begin
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output_state_next = OUTPUT_STATE_SEGMENT;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (rst) begin
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input_state_reg <= INPUT_STATE_IDLE;
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output_state_reg <= OUTPUT_STATE_IDLE;
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end else begin
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input_state_reg <= input_state_next;
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output_state_reg <= output_state_next;
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end
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input_count_reg <= input_count_next;
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output_count_reg <= output_count_next;
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fail_frame_reg <= fail_frame_next;
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end
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// output datapath logic
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reg [7:0] m_axis_tdata_reg = 8'd0;
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reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
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reg m_axis_tlast_reg = 1'b0;
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reg m_axis_tuser_reg = 1'b0;
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reg [7:0] temp_m_axis_tdata_reg = 8'd0;
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reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
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reg temp_m_axis_tlast_reg = 1'b0;
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reg temp_m_axis_tuser_reg = 1'b0;
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// datapath control
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reg store_axis_int_to_output;
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reg store_axis_int_to_temp;
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reg store_axis_temp_to_output;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign m_axis_tlast = m_axis_tlast_reg;
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assign m_axis_tuser = m_axis_tuser_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
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always @* begin
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// transfer sink ready state to source
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m_axis_tvalid_next = m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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store_axis_int_to_output = 1'b0;
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store_axis_int_to_temp = 1'b0;
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store_axis_temp_to_output = 1'b0;
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if (m_axis_tready_int_reg) begin
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// input is ready
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if (m_axis_tready || !m_axis_tvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axis_tvalid_next = m_axis_tvalid_int;
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store_axis_int_to_temp = 1'b1;
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end
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end else if (m_axis_tready) begin
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// input is not ready, but output is ready
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m_axis_tvalid_next = temp_m_axis_tvalid_reg;
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temp_m_axis_tvalid_next = 1'b0;
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store_axis_temp_to_output = 1'b1;
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|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (rst) begin
|
|
m_axis_tvalid_reg <= 1'b0;
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|
m_axis_tready_int_reg <= 1'b0;
|
|
temp_m_axis_tvalid_reg <= 1'b0;
|
|
end else begin
|
|
m_axis_tvalid_reg <= m_axis_tvalid_next;
|
|
m_axis_tready_int_reg <= m_axis_tready_int_early;
|
|
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
|
|
end
|
|
|
|
// datapath
|
|
if (store_axis_int_to_output) begin
|
|
m_axis_tdata_reg <= m_axis_tdata_int;
|
|
m_axis_tlast_reg <= m_axis_tlast_int;
|
|
m_axis_tuser_reg <= m_axis_tuser_int;
|
|
end else if (store_axis_temp_to_output) begin
|
|
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
|
|
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
|
|
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
|
|
end
|
|
|
|
if (store_axis_int_to_temp) begin
|
|
temp_m_axis_tdata_reg <= m_axis_tdata_int;
|
|
temp_m_axis_tlast_reg <= m_axis_tlast_int;
|
|
temp_m_axis_tuser_reg <= m_axis_tuser_int;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|