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corundum/fpga/mqnic
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Alex Forencich 2a10dc1582 fpga/mqnic/S10MX_DK: Annotate serdes pins in QSF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-23 19:43:21 -07:00
..
250_SoC
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
ADM_PCIE_9V3
Rename cmac_ts_insert to mac_ts_insert
2022-07-18 22:27:27 -07:00
AU50
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
AU200
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
AU250
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
AU280
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
DE10_Agilex
Add 100G mqnic design for DE10-Agilex
2022-07-21 18:49:35 -07:00
DNPCIe_40G_KU_LL_2QSFP/fpga
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
fb2CG
Rename cmac_ts_insert to mac_ts_insert
2022-07-18 22:27:27 -07:00
NetFPGA_SUME/fpga
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
Nexus_K3P_Q/fpga_25g
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
Nexus_K3P_S/fpga_25g
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
Nexus_K35_S/fpga
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
S10DX_DK/fpga_25g
Add 25g mqnic design for Stratix 10 DX dev kit
2022-07-23 19:42:58 -07:00
S10MX_DK/fpga_10g
fpga/mqnic/S10MX_DK: Annotate serdes pins in QSF
2022-07-23 19:43:21 -07:00
VCU108/fpga_10g
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00
VCU118
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
VCU1525
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
XUPP3R
25G designs use double width sync datapath by default
2022-07-18 23:31:36 -07:00
ZCU106
Add stretched PTP PPS output
2022-07-18 22:25:58 -07:00