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corundum/fpga/mqnic/AU200/fpga_25g
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Alex Forencich 2a7d0e0947 Use new PTP time distribution subsystem 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2023-11-07 21:57:07 -08:00
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common
Update Vivado makefiles
2023-07-13 18:45:01 -07:00
fpga_AU200
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
fpga_AU200_10g
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
fpga_AU250
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
fpga_AU250_10g
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
fpga_VCU1525
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
fpga_VCU1525_10g
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
ip
fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances
2023-09-05 23:44:12 -07:00
rtl
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
tb/fpga_core
Use new PTP time distribution subsystem
2023-11-07 21:57:07 -08:00
app
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
boot.xdc
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
cfgmclk.xdc
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
fpga.xdc
fpga/mqnic: Merge AU200, AU250, and VCU1525 designs
2023-10-12 23:26:08 -07:00
lib
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
Makefile
Unified 10G/25G design for AU200
2022-03-14 21:38:31 -07:00
placement_au200.xdc
fpga/mqnic: Merge AU200, AU250, and VCU1525 designs
2023-10-12 23:26:08 -07:00
placement_au250.xdc
fpga/mqnic: Merge AU200, AU250, and VCU1525 designs
2023-10-12 23:26:08 -07:00
placement_vcu1525.xdc
fpga/mqnic: Merge AU200, AU250, and VCU1525 designs
2023-10-12 23:26:08 -07:00
README.md
fpga/mqnic: Merge AU200, AU250, and VCU1525 designs
2023-10-12 23:26:08 -07:00

README.md

Corundum mqnic for Alveo U200/Alveo U250/VCU1525

Introduction

This design targets the Xilinx Alveo U200/Alveo U250/VCU1525 FPGA board.

  • FPGA
    • AU200: xcu200-fsgd2104-2-e
    • AU250: xcu250-fsgd2104-2-e
    • VCU1525: xcvu9p-fsgd2104-2L-e
  • PHY: 10G BASE-R PHY IP core and internal GTY transceiver
  • RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)

Quick start

Build FPGA bitstream

Run make in the fpga subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.

Build driver and userspace tools

On the host system, run make in modules/mqnic to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then, run make in utils to build the userspace tools.

Testing

Run make program to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with insmod mqnic.ko. Check dmesg for output from driver initialization, and run mqnic-dump -d /dev/mqnic0 to dump the internal state.