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corundum/fpga/mqnic/AU50/fpga_100g/rtl
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Alex Forencich e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-18 22:24:41 -07:00
..
common
Add 100G mqnic design for Alveo U50
2020-07-17 01:44:59 -07:00
fpga_core.v
Separate PTP TX clock input
2022-07-18 22:24:41 -07:00
fpga.v
Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices
2022-07-08 22:07:18 -07:00
sync_signal.v
Add default_nettype none and resetall directives
2021-10-20 21:53:39 -07:00