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corundum/fpga/common/rtl
History
Alex Forencich c6e75b40a1 Don't need AXI DMA unaligned support
2019-09-23 18:11:25 -07:00
..
cpl_op_mux.v
Add completion op mux module
2019-09-23 14:47:09 -07:00
cpl_queue_manager.v
Fix pipelining bug
2019-09-13 13:48:48 -07:00
cpl_write.v
Add completion write module
2019-09-23 14:44:08 -07:00
desc_fetch.v
Add descriptor fetch module
2019-09-23 14:41:35 -07:00
desc_op_mux.v
Add descriptor op mux module
2019-09-23 14:47:00 -07:00
event_mux.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
event_queue.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
interface.v
Pull out descriptor and completion handling logic
2019-09-23 18:10:35 -07:00
port.v
Don't need AXI DMA unaligned support
2019-09-23 18:11:25 -07:00
queue_manager.v
Fix pipelining bug
2019-09-13 13:48:48 -07:00
rx_checksum.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
rx_engine.v
Pull out descriptor and completion handling logic
2019-09-23 18:10:35 -07:00
tdma_ber_ch.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_ber.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tdma_scheduler.v
Parameter updates and documentation
2019-07-27 23:47:46 -07:00
tx_checksum.v
Fix latch inference
2019-08-29 18:36:15 -07:00
tx_engine.v
Pull out descriptor and completion handling logic
2019-09-23 18:10:35 -07:00
tx_scheduler_rr.v
Improve tx_scheduler_rr timing
2019-09-14 23:32:34 -07:00
tx_scheduler_tdma_rr.v
Truncate high order address bits
2019-08-13 00:41:10 -07:00