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130 lines
3.6 KiB
ReStructuredText
130 lines
3.6 KiB
ReStructuredText
.. _mod_mqnic_ptp:
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=============
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``mqnic_ptp``
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=============
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``mqnic_ptp`` implements the PTP subsystem, including PTP clock and period output modules.
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``mqnic_ptp`` integrates the following modules:
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* :ref:`mod_mqnic_ptp_clock`: PTP clock (:ref:`rb_phc`)
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* :ref:`mod_mqnic_ptp_perout`: PTP period output (:ref:`rb_phc_perout`)
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Parameters
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==========
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.. object:: PTP_PERIOD_NS_WIDTH
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PTP period ns field width, default ``4``.
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.. object:: PTP_OFFSET_NS_WIDTH
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PTP offset ns field width, default ``32``.
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.. object:: PTP_FNS_WIDTH
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PTP fractional ns field width, default ``32``.
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.. object:: PTP_PERIOD_NS
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PTP nominal period, ns portion ``4'd4``.
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.. object:: PTP_PERIOD_FNS
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PTP nominal period, fractional ns portion ``32'd0``.
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.. object:: PTP_PEROUT_ENABLE
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Enable PTP period output module, default ``0``.
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.. object:: PTP_PEROUT_COUNT
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Number of PTP period output channels, default ``1``.
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.. object:: REG_ADDR_WIDTH
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Register interface address width, default ``7+(PTP_PEROUT_ENABLE ? $clog2((PTP_PEROUT_COUNT+1)/2) + 1 : 0)``.
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.. object:: REG_DATA_WIDTH
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Register interface data width, default ``32``.
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.. object:: REG_STRB_WIDTH
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Register interface byte enable width, must be set to ``(REG_DATA_WIDTH/8)``.
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.. object:: RB_BASE_ADDR
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Base address of control register block, default ``0``.
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.. object:: RB_NEXT_PTR
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Address of next control register block, default ``0``.
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Ports
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=====
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.. object:: clk
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Logic clock.
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.. table::
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====== === ===== ==================
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Signal Dir Width Description
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====== === ===== ==================
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clk in 1 Logic clock
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====== === ===== ==================
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.. object:: rst
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Logic reset, active high
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.. table::
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====== === ===== ==================
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Signal Dir Width Description
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====== === ===== ==================
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rst in 1 Logic reset, active high
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====== === ===== ==================
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.. object:: reg
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Control register interface
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.. table::
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=========== === =============== ===================
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Signal Dir Width Description
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=========== === =============== ===================
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reg_wr_addr in REG_ADDR_WIDTH Write address
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reg_wr_data in REG_DATA_WIDTH Write data
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reg_wr_strb in REG_STRB_WIDTH Write byte enable
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reg_wr_en in 1 Write enable
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reg_wr_wait out 1 Write wait
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reg_wr_ack out 1 Write acknowledge
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reg_rd_addr in REG_ADDR_WIDTH Read address
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reg_rd_en in 1 Read enable
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reg_rd_data out REG_DATA_WIDTH Read data
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reg_rd_wait out 1 Read wait
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reg_rd_ack out 1 Read acknowledge
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=========== === =============== ===================
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.. object:: ptp
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PTP signals
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.. table::
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================= === ================ ===================
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Signal Dir Width Description
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================= === ================ ===================
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ptp_pps out 1 Pulse-per-second
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ptp_ts_96 out 96 PTP timestamp
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ptp_ts_step out 1 PTP timestamp step
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ptp_perout_locked out PTP_PEROUT_COUNT Period output channel locked
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ptp_perout_error out PTP_PEROUT_COUNT Period output channel error
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ptp_perout_pulse out PTP_PEROUT_COUNT Period output channel pulse
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================= === ================ ===================
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