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331 lines
11 KiB
Verilog
331 lines
11 KiB
Verilog
// SPDX-License-Identifier: BSD-2-Clause-Views
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/*
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* Copyright (c) 2019-2023 The Regents of the University of California
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Receive hashing module
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*/
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module rx_hash #
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(
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// Width of AXI stream interfaces in bits
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parameter DATA_WIDTH = 256,
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// AXI stream tkeep signal width (words per cycle)
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] s_axis_tdata,
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input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
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input wire s_axis_tvalid,
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input wire s_axis_tlast,
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/*
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* Control
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*/
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input wire [40*8-1:0] hash_key,
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/*
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* Hash output
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*/
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output wire [31:0] m_axis_hash,
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output wire [3:0] m_axis_hash_type,
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output wire m_axis_hash_valid
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);
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parameter CYCLE_COUNT = (38+KEEP_WIDTH-1)/KEEP_WIDTH;
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parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
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// bus width assertions
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initial begin
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if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
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$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
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$finish;
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end
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end
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/*
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TCP/UDP Frame (IPv4)
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x0800) 2 octets
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Version (4) 4 bits
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IHL (5-15) 4 bits
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DSCP (0) 6 bits
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ECN (0) 2 bits
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length 2 octets
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identification (0?) 2 octets
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flags (010) 3 bits
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fragment offset (0) 13 bits
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time to live (64?) 1 octet
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protocol (6 or 17) 1 octet
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header checksum 2 octets
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source IP 4 octets
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destination IP 4 octets
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options (IHL-5)*4 octets
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source port 2 octets
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desination port 2 octets
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other fields + payload
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TCP/UDP Frame (IPv6)
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Field Length
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Destination MAC address 6 octets
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Source MAC address 6 octets
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Ethertype (0x86dd) 2 octets
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Version (4) 4 bits
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Traffic class 8 bits
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Flow label 20 bits
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length 2 octets
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next header (6 or 17) 1 octet
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hop limit 1 octet
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source IP 16 octets
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destination IP 16 octets
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source port 2 octets
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desination port 2 octets
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other fields + payload
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*/
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reg active_reg = 1'b1, active_next;
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reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
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reg [15:0] eth_type_reg = 15'd0, eth_type_next;
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reg [3:0] ihl_reg = 4'd0, ihl_next;
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reg [36*8-1:0] hash_data_reg = 0, hash_data_next;
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reg hash_data_ipv4_reg = 1'b0, hash_data_ipv4_next;
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reg hash_data_tcp_reg = 1'b0, hash_data_tcp_next;
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reg hash_data_udp_reg = 1'b0, hash_data_udp_next;
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reg [3:0] hash_data_type_reg = 4'b0000, hash_data_type_next;
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reg hash_data_valid_reg = 0, hash_data_valid_next;
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reg [31:0] hash_part_ipv4_ip_reg = 32'd0;
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reg [31:0] hash_part_ipv4_port_reg = 32'd0;
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reg hash_part_ipv4_reg = 0;
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reg hash_part_tcp_reg = 0;
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reg hash_part_udp_reg = 0;
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reg [3:0] hash_part_type_reg = 4'b0000;
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reg hash_part_valid_reg = 0;
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reg [31:0] hash_reg = 32'd0;
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reg [3:0] hash_type_reg = 4'b0000;
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reg hash_valid_reg = 0;
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assign m_axis_hash = hash_reg;
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assign m_axis_hash_type = hash_type_reg;
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assign m_axis_hash_valid = hash_valid_reg;
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function [31:0] hash_toep(input [36*8-1:0] data, input [5:0] len, input [40*8-1:0] key);
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integer i, j;
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begin
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hash_toep = 0;
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for (i = 0; i < len; i = i + 1) begin
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for (j = 0; j < 8; j = j + 1) begin
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if (data[i*8 + (7-j)]) begin
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hash_toep = hash_toep ^ key[40*8 - 32 - i*8 - j +: 32];
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end
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end
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end
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end
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endfunction
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// compute toeplitz hashes
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wire [31:0] hash_part_ipv4_ip = hash_toep(hash_data_reg, 8, hash_key);
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wire [31:0] hash_part_ipv4_port = hash_toep(hash_data_reg >> 8*8, 4, hash_key << 8*8);
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always @* begin
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active_next = active_reg;
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ptr_next = ptr_reg;
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eth_type_next = eth_type_reg;
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ihl_next = ihl_reg;
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hash_data_next = hash_data_reg;
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hash_data_ipv4_next = hash_data_ipv4_reg;
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hash_data_tcp_next = hash_data_tcp_reg;
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hash_data_udp_next = hash_data_udp_reg;
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hash_data_type_next = hash_data_type_reg;
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hash_data_valid_next = 1'b0;
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if (s_axis_tvalid) begin
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if (active_reg) begin
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ptr_next = ptr_reg + 1;
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if (ptr_reg == 0) begin
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hash_data_ipv4_next = 1'b0;
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hash_data_tcp_next = 1'b0;
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hash_data_udp_next = 1'b0;
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end
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if (ptr_reg == 12/KEEP_WIDTH) begin
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// eth type MSB
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eth_type_next[15:8] = s_axis_tdata[(12%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 13/KEEP_WIDTH) begin
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// eth type LSB
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eth_type_next[7:0] = s_axis_tdata[(13%KEEP_WIDTH)*8 +: 8];
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// check eth type
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if (eth_type_next == 16'h0800) begin
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// ipv4
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hash_data_ipv4_next = 1'b1;
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end else if (eth_type_next == 16'h86dd) begin
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// ipv6
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// TODO
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end else begin
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// other
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hash_data_type_next = 4'b0000;
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hash_data_valid_next = 1'b1;
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active_next = 1'b0;
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end
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end
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if (ptr_reg == 14/KEEP_WIDTH) begin
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// capture IHL
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ihl_next = s_axis_tdata[(14%KEEP_WIDTH)*8 +: 8];
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end
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if (hash_data_ipv4_next) begin
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if (ptr_reg == 23/KEEP_WIDTH) begin
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// capture protocol
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if (s_axis_tdata[(23%KEEP_WIDTH)*8 +: 8] == 8'h06 && ihl_next == 5) begin
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// TCP
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hash_data_tcp_next = 1'b1;
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end else if (s_axis_tdata[(23%KEEP_WIDTH)*8 +: 8] == 8'h11 && ihl_next == 5) begin
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// UDP
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hash_data_udp_next = 1'b1;
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end
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end
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if (ptr_reg == 26/KEEP_WIDTH) begin
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// capture source IP
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hash_data_next[7:0] = s_axis_tdata[(26%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 27/KEEP_WIDTH) begin
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// capture source IP
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hash_data_next[15:8] = s_axis_tdata[(27%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 28/KEEP_WIDTH) begin
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// capture source IP
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hash_data_next[23:16] = s_axis_tdata[(28%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 29/KEEP_WIDTH) begin
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// capture source IP
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hash_data_next[31:24] = s_axis_tdata[(29%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 30/KEEP_WIDTH) begin
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// capture dest IP
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hash_data_next[39:32] = s_axis_tdata[(30%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 31/KEEP_WIDTH) begin
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// capture dest IP
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hash_data_next[47:40] = s_axis_tdata[(31%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 32/KEEP_WIDTH) begin
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// capture dest IP
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hash_data_next[55:48] = s_axis_tdata[(32%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 33/KEEP_WIDTH) begin
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// capture dest IP
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hash_data_next[63:56] = s_axis_tdata[(33%KEEP_WIDTH)*8 +: 8];
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if (!(hash_data_tcp_next || hash_data_udp_next)) begin
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hash_data_type_next = {1'b0, 1'b0, 1'b0, 1'b1};
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hash_data_valid_next = 1'b1;
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active_next = 1'b0;
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end
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end
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if (hash_data_tcp_next || hash_data_udp_next) begin
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// TODO IHL (skip options)
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if (ptr_reg == 34/KEEP_WIDTH) begin
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// capture source port
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hash_data_next[71:64] = s_axis_tdata[(34%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 35/KEEP_WIDTH) begin
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// capture source port
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hash_data_next[79:72] = s_axis_tdata[(35%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 36/KEEP_WIDTH) begin
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// capture dest port
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hash_data_next[87:80] = s_axis_tdata[(36%KEEP_WIDTH)*8 +: 8];
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end
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if (ptr_reg == 37/KEEP_WIDTH) begin
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// capture dest port
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hash_data_next[95:88] = s_axis_tdata[(37%KEEP_WIDTH)*8 +: 8];
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hash_data_type_next = {hash_data_udp_next, hash_data_tcp_next, 1'b0, 1'b1};
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hash_data_valid_next = 1'b1;
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active_next = 1'b0;
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end
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end
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end
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end
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if (s_axis_tlast) begin
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if (active_next) begin
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hash_data_type_next = 4'b0000;
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hash_data_valid_next = 1'b1;
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end
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ptr_next = 0;
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active_next = 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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active_reg <= active_next;
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ptr_reg <= ptr_next;
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eth_type_reg <= eth_type_next;
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ihl_reg <= ihl_next;
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hash_data_reg <= hash_data_next;
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hash_data_ipv4_reg <= hash_data_ipv4_next;
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hash_data_tcp_reg <= hash_data_tcp_next;
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hash_data_udp_reg <= hash_data_udp_next;
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hash_data_type_reg <= hash_data_type_next;
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hash_data_valid_reg <= hash_data_valid_next;
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hash_part_ipv4_ip_reg <= hash_part_ipv4_ip;
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hash_part_ipv4_port_reg <= hash_part_ipv4_port;
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hash_part_ipv4_reg <= hash_data_ipv4_reg;
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hash_part_tcp_reg <= hash_data_tcp_reg;
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hash_part_udp_reg <= hash_data_udp_reg;
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hash_part_type_reg <= hash_data_type_reg;
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hash_part_valid_reg <= hash_data_valid_reg;
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if (hash_part_ipv4_reg) begin
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if (hash_part_tcp_reg || hash_part_udp_reg) begin
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hash_reg <= hash_part_ipv4_ip_reg ^ hash_part_ipv4_port_reg;
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end else begin
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hash_reg <= hash_part_ipv4_ip_reg;
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end
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end else begin
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hash_reg <= 0;
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end
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hash_type_reg <= hash_part_type_reg;
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hash_valid_reg <= hash_part_valid_reg;
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if (rst) begin
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active_reg <= 1'b1;
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ptr_reg <= 0;
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hash_data_valid_reg <= 0;
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end
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end
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endmodule
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`resetall
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